Thermal-Aware Application Scheduling on Device-Heterogeneous Embedded Architectures

Karthik Swaminathan, Jagadish Kotra, Huichu Liu, John Morgan Sampson, Mahmut Kandemir, Vijaykrishnan Narayanan

Research output: Contribution to journalConference article

5 Citations (Scopus)

Abstract

The challenges of the Power Wall manifest in mobile and embedded processors due to their inherent thermal and formfactor constraints. The power dissipated over a fixed area, namely, the power density, directly affects acceptable core temperatures even for low-power devices. In this paper, we examine techniques to counter this power density increase with device and microarchitecture-level heterogeneity. We explore the design space in which various parameters such as frequency and microarchitectural complexity can be traded off against each other in order to achieve the optimal configuration for a fixed temperature limit. Since conventional CMOS technology based cores may not satisfy our performance and power requirements, especially under tight thermal constraints, we propose a heterogeneous CMOS-Tunnel FET multicore for obtaining the optimal operating points under power and thermal limitations. Using a profiling based static assignment scheme, we demonstrate the improvement obtained by coupling this device-level heterogeneity to architectural modifications. We also propose an instruction slack-based scheme to map applications on the heterogeneous multicore. Our schemes show an improvement of up to 47% performance and 30% energy above the best homogeneous configuration.

Original languageEnglish (US)
Article number7031736
Pages (from-to)221-226
Number of pages6
JournalProceedings of the IEEE International Conference on VLSI Design
Volume2015-February
Issue numberFebruary
DOIs
StatePublished - Feb 4 2015
Event28th International Conference on VLSI Design, VLSID 2015 - held concurrently with the 14th International Conference on Embedded Systems - Bangalore, India
Duration: Jan 3 2015Jan 7 2015

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Scheduling
Field effect transistors
Tunnels
Temperature
Hot Temperature

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

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title = "Thermal-Aware Application Scheduling on Device-Heterogeneous Embedded Architectures",
abstract = "The challenges of the Power Wall manifest in mobile and embedded processors due to their inherent thermal and formfactor constraints. The power dissipated over a fixed area, namely, the power density, directly affects acceptable core temperatures even for low-power devices. In this paper, we examine techniques to counter this power density increase with device and microarchitecture-level heterogeneity. We explore the design space in which various parameters such as frequency and microarchitectural complexity can be traded off against each other in order to achieve the optimal configuration for a fixed temperature limit. Since conventional CMOS technology based cores may not satisfy our performance and power requirements, especially under tight thermal constraints, we propose a heterogeneous CMOS-Tunnel FET multicore for obtaining the optimal operating points under power and thermal limitations. Using a profiling based static assignment scheme, we demonstrate the improvement obtained by coupling this device-level heterogeneity to architectural modifications. We also propose an instruction slack-based scheme to map applications on the heterogeneous multicore. Our schemes show an improvement of up to 47{\%} performance and 30{\%} energy above the best homogeneous configuration.",
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Thermal-Aware Application Scheduling on Device-Heterogeneous Embedded Architectures. / Swaminathan, Karthik; Kotra, Jagadish; Liu, Huichu; Sampson, John Morgan; Kandemir, Mahmut; Narayanan, Vijaykrishnan.

In: Proceedings of the IEEE International Conference on VLSI Design, Vol. 2015-February, No. February, 7031736, 04.02.2015, p. 221-226.

Research output: Contribution to journalConference article

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