Abstract
The challenges of the Power Wall manifest in mobile and embedded processors due to their inherent thermal and formfactor constraints. The power dissipated over a fixed area, namely, the power density, directly affects acceptable core temperatures even for low-power devices. In this paper, we examine techniques to counter this power density increase with device and microarchitecture-level heterogeneity. We explore the design space in which various parameters such as frequency and microarchitectural complexity can be traded off against each other in order to achieve the optimal configuration for a fixed temperature limit. Since conventional CMOS technology based cores may not satisfy our performance and power requirements, especially under tight thermal constraints, we propose a heterogeneous CMOS-Tunnel FET multicore for obtaining the optimal operating points under power and thermal limitations. Using a profiling based static assignment scheme, we demonstrate the improvement obtained by coupling this device-level heterogeneity to architectural modifications. We also propose an instruction slack-based scheme to map applications on the heterogeneous multicore. Our schemes show an improvement of up to 47% performance and 30% energy above the best homogeneous configuration.
| Original language | English (US) |
|---|---|
| Article number | 7031736 |
| Pages (from-to) | 221-226 |
| Number of pages | 6 |
| Journal | Proceedings of the IEEE International Conference on VLSI Design |
| Volume | 2015-February |
| Issue number | February |
| DOIs | |
| State | Published - Feb 4 2015 |
| Event | 28th International Conference on VLSI Design, VLSID 2015 - held concurrently with the 14th International Conference on Embedded Systems - Bangalore, India Duration: Jan 3 2015 → Jan 7 2015 |
Fingerprint
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
}
Thermal-Aware Application Scheduling on Device-Heterogeneous Embedded Architectures. / Swaminathan, Karthik; Kotra, Jagadish; Liu, Huichu; Sampson, John Morgan; Kandemir, Mahmut; Narayanan, Vijaykrishnan.
In: Proceedings of the IEEE International Conference on VLSI Design, Vol. 2015-February, No. February, 7031736, 04.02.2015, p. 221-226.Research output: Contribution to journal › Conference article
TY - JOUR
T1 - Thermal-Aware Application Scheduling on Device-Heterogeneous Embedded Architectures
AU - Swaminathan, Karthik
AU - Kotra, Jagadish
AU - Liu, Huichu
AU - Sampson, John Morgan
AU - Kandemir, Mahmut
AU - Narayanan, Vijaykrishnan
PY - 2015/2/4
Y1 - 2015/2/4
N2 - The challenges of the Power Wall manifest in mobile and embedded processors due to their inherent thermal and formfactor constraints. The power dissipated over a fixed area, namely, the power density, directly affects acceptable core temperatures even for low-power devices. In this paper, we examine techniques to counter this power density increase with device and microarchitecture-level heterogeneity. We explore the design space in which various parameters such as frequency and microarchitectural complexity can be traded off against each other in order to achieve the optimal configuration for a fixed temperature limit. Since conventional CMOS technology based cores may not satisfy our performance and power requirements, especially under tight thermal constraints, we propose a heterogeneous CMOS-Tunnel FET multicore for obtaining the optimal operating points under power and thermal limitations. Using a profiling based static assignment scheme, we demonstrate the improvement obtained by coupling this device-level heterogeneity to architectural modifications. We also propose an instruction slack-based scheme to map applications on the heterogeneous multicore. Our schemes show an improvement of up to 47% performance and 30% energy above the best homogeneous configuration.
AB - The challenges of the Power Wall manifest in mobile and embedded processors due to their inherent thermal and formfactor constraints. The power dissipated over a fixed area, namely, the power density, directly affects acceptable core temperatures even for low-power devices. In this paper, we examine techniques to counter this power density increase with device and microarchitecture-level heterogeneity. We explore the design space in which various parameters such as frequency and microarchitectural complexity can be traded off against each other in order to achieve the optimal configuration for a fixed temperature limit. Since conventional CMOS technology based cores may not satisfy our performance and power requirements, especially under tight thermal constraints, we propose a heterogeneous CMOS-Tunnel FET multicore for obtaining the optimal operating points under power and thermal limitations. Using a profiling based static assignment scheme, we demonstrate the improvement obtained by coupling this device-level heterogeneity to architectural modifications. We also propose an instruction slack-based scheme to map applications on the heterogeneous multicore. Our schemes show an improvement of up to 47% performance and 30% energy above the best homogeneous configuration.
UR - http://www.scopus.com/inward/record.url?scp=84938265227&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84938265227&partnerID=8YFLogxK
U2 - 10.1109/VLSID.2015.43
DO - 10.1109/VLSID.2015.43
M3 - Conference article
VL - 2015-February
SP - 221
EP - 226
JO - Proceedings of the IEEE International Conference on VLSI Design
JF - Proceedings of the IEEE International Conference on VLSI Design
SN - 1063-9667
IS - February
M1 - 7031736
ER -