TY - GEN
T1 - Thermal-Aware Application Scheduling on Device-Heterogeneous Embedded Architectures
AU - Swaminathan, Karthik
AU - Kotra, Jagadish
AU - Liu, Huichu
AU - Sampson, Jack
AU - Kandemir, Mahmut
AU - Narayanan, Vijaykrishnan
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/2/4
Y1 - 2015/2/4
N2 - The challenges of the Power Wall manifest in mobile and embedded processors due to their inherent thermal and formfactor constraints. The power dissipated over a fixed area, namely, the power density, directly affects acceptable core temperatures even for low-power devices. In this paper, we examine techniques to counter this power density increase with device and microarchitecture-level heterogeneity. We explore the design space in which various parameters such as frequency and microarchitectural complexity can be traded off against each other in order to achieve the optimal configuration for a fixed temperature limit. Since conventional CMOS technology based cores may not satisfy our performance and power requirements, especially under tight thermal constraints, we propose a heterogeneous CMOS-Tunnel FET multicore for obtaining the optimal operating points under power and thermal limitations. Using a profiling based static assignment scheme, we demonstrate the improvement obtained by coupling this device-level heterogeneity to architectural modifications. We also propose an instruction slack-based scheme to map applications on the heterogeneous multicore. Our schemes show an improvement of up to 47% performance and 30% energy above the best homogeneous configuration.
AB - The challenges of the Power Wall manifest in mobile and embedded processors due to their inherent thermal and formfactor constraints. The power dissipated over a fixed area, namely, the power density, directly affects acceptable core temperatures even for low-power devices. In this paper, we examine techniques to counter this power density increase with device and microarchitecture-level heterogeneity. We explore the design space in which various parameters such as frequency and microarchitectural complexity can be traded off against each other in order to achieve the optimal configuration for a fixed temperature limit. Since conventional CMOS technology based cores may not satisfy our performance and power requirements, especially under tight thermal constraints, we propose a heterogeneous CMOS-Tunnel FET multicore for obtaining the optimal operating points under power and thermal limitations. Using a profiling based static assignment scheme, we demonstrate the improvement obtained by coupling this device-level heterogeneity to architectural modifications. We also propose an instruction slack-based scheme to map applications on the heterogeneous multicore. Our schemes show an improvement of up to 47% performance and 30% energy above the best homogeneous configuration.
UR - http://www.scopus.com/inward/record.url?scp=84938265227&partnerID=8YFLogxK
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U2 - 10.1109/VLSID.2015.43
DO - 10.1109/VLSID.2015.43
M3 - Conference contribution
AN - SCOPUS:84938265227
T3 - Proceedings of the IEEE International Conference on VLSI Design
SP - 221
EP - 226
BT - Proceedings of the 28th International Conference on VLSI Design, VLSID 2015 - held concurrently with the 14th International Conference on Embedded Systems
PB - IEEE Computer Society
T2 - 28th International Conference on VLSI Design, VLSID 2015 - held concurrently with the 14th International Conference on Embedded Systems
Y2 - 3 January 2015 through 7 January 2015
ER -