Abstract
In this work, we present a genetic algorithm based thermal-aware floorplanning framework that aims at reducing hot spots and distributing temperature evenly across a chip while optimizing the traditional design metric, chip area. The floorplanning problem is formulated as a genetic algorithm problem, and a tool called HotSpot is used to calculate floorplanning temperature based on the power dissipation, the physical dimension, and the location of modules. Area and/or temperature optimizations guide the genetic algorithm to generate the final fittest solution. The experimental results using MCNC benchmarks and a face detection chip show that our combined area and thermal optimization technique decreases the peak temperature sufficiently while providing floorplans that are as compact as the traditional area-oriented techniques.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - 6th International Symposium on Quality Electronic Design, ISQED 2005 |
| Pages | 634-639 |
| Number of pages | 6 |
| DOIs | |
| State | Published - Dec 1 2005 |
| Event | 6th International Symposium on Quality Electronic Design, ISQED 2005 - San Jose, CA, United States Duration: Mar 21 2005 → Mar 23 2005 |
Publication series
| Name | Proceedings - International Symposium on Quality Electronic Design, ISQED |
|---|---|
| ISSN (Print) | 1948-3287 |
| ISSN (Electronic) | 1948-3295 |
Other
| Other | 6th International Symposium on Quality Electronic Design, ISQED 2005 |
|---|---|
| Country | United States |
| City | San Jose, CA |
| Period | 3/21/05 → 3/23/05 |
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality
Cite this
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Thermal-aware floorplanning using genetic algorithms. / Hung, W. L.; Xie, Y.; Narayanan, Vijaykrishnan; Addo-Quaye, C.; Theocharides, T.; Irwin, Mary Jane.
Proceedings - 6th International Symposium on Quality Electronic Design, ISQED 2005. 2005. p. 634-639 1410656 (Proceedings - International Symposium on Quality Electronic Design, ISQED).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Thermal-aware floorplanning using genetic algorithms
AU - Hung, W. L.
AU - Xie, Y.
AU - Narayanan, Vijaykrishnan
AU - Addo-Quaye, C.
AU - Theocharides, T.
AU - Irwin, Mary Jane
PY - 2005/12/1
Y1 - 2005/12/1
N2 - In this work, we present a genetic algorithm based thermal-aware floorplanning framework that aims at reducing hot spots and distributing temperature evenly across a chip while optimizing the traditional design metric, chip area. The floorplanning problem is formulated as a genetic algorithm problem, and a tool called HotSpot is used to calculate floorplanning temperature based on the power dissipation, the physical dimension, and the location of modules. Area and/or temperature optimizations guide the genetic algorithm to generate the final fittest solution. The experimental results using MCNC benchmarks and a face detection chip show that our combined area and thermal optimization technique decreases the peak temperature sufficiently while providing floorplans that are as compact as the traditional area-oriented techniques.
AB - In this work, we present a genetic algorithm based thermal-aware floorplanning framework that aims at reducing hot spots and distributing temperature evenly across a chip while optimizing the traditional design metric, chip area. The floorplanning problem is formulated as a genetic algorithm problem, and a tool called HotSpot is used to calculate floorplanning temperature based on the power dissipation, the physical dimension, and the location of modules. Area and/or temperature optimizations guide the genetic algorithm to generate the final fittest solution. The experimental results using MCNC benchmarks and a face detection chip show that our combined area and thermal optimization technique decreases the peak temperature sufficiently while providing floorplans that are as compact as the traditional area-oriented techniques.
UR - http://www.scopus.com/inward/record.url?scp=84886688297&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84886688297&partnerID=8YFLogxK
U2 - 10.1109/ISQED.2005.122
DO - 10.1109/ISQED.2005.122
M3 - Conference contribution
SN - 0769523013
SN - 9780769523019
T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED
SP - 634
EP - 639
BT - Proceedings - 6th International Symposium on Quality Electronic Design, ISQED 2005
ER -