Thermal gradient aware clock skew scheduling for FPGAs

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

FPGAs are gradually becoming an essential flexible-digital solution for automotive and military applications, where operating at extreme ambient temperature conditions reaching 125°C are not uncommon. Operating FPGAs under such high-temperature environments require adequate timing margin to compensate potential delay increase, which worsens the performance of FPGAs. To minimize the performance degradation, we propose a thermal gradient aware clock skew scheduling technique which allocates temperature-adaptive timing margins considering worst case thermal gradients and junction temperature ranges of logic-paths in the design, instead of assigning a worst case timing margin to the entire design. The experimental results shows that our technique extends the operating ambient temperature range with an average about 20% performance im-provement1.

Original languageEnglish (US)
Title of host publicationProceedings - 2010 International Conference on Field Programmable Logic and Applications, FPL 2010
Pages101-106
Number of pages6
DOIs
StatePublished - Dec 1 2010
Event20th International Conference on Field Programmable Logic and Applications, FPL 2010 - Milano, Italy
Duration: Aug 31 2010Sep 2 2010

Other

Other20th International Conference on Field Programmable Logic and Applications, FPL 2010
CountryItaly
CityMilano
Period8/31/109/2/10

Fingerprint

Thermal gradients
Field programmable gate arrays (FPGA)
Clocks
Scheduling
Temperature
Military applications
Degradation

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Hardware and Architecture

Cite this

Bae, S., & Narayanan, V. (2010). Thermal gradient aware clock skew scheduling for FPGAs. In Proceedings - 2010 International Conference on Field Programmable Logic and Applications, FPL 2010 (pp. 101-106). [5694228] https://doi.org/10.1109/FPL.2010.29
Bae, Sungmin ; Narayanan, Vijaykrishnan. / Thermal gradient aware clock skew scheduling for FPGAs. Proceedings - 2010 International Conference on Field Programmable Logic and Applications, FPL 2010. 2010. pp. 101-106
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Bae, S & Narayanan, V 2010, Thermal gradient aware clock skew scheduling for FPGAs. in Proceedings - 2010 International Conference on Field Programmable Logic and Applications, FPL 2010., 5694228, pp. 101-106, 20th International Conference on Field Programmable Logic and Applications, FPL 2010, Milano, Italy, 8/31/10. https://doi.org/10.1109/FPL.2010.29

Thermal gradient aware clock skew scheduling for FPGAs. / Bae, Sungmin; Narayanan, Vijaykrishnan.

Proceedings - 2010 International Conference on Field Programmable Logic and Applications, FPL 2010. 2010. p. 101-106 5694228.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Bae S, Narayanan V. Thermal gradient aware clock skew scheduling for FPGAs. In Proceedings - 2010 International Conference on Field Programmable Logic and Applications, FPL 2010. 2010. p. 101-106. 5694228 https://doi.org/10.1109/FPL.2010.29