Threshold defined camouflaged gates in 65nm technology for reverse engineering protection

Anirudh S. Iyengar, Deepak Vontela, Ithihasa Reddy, Swaroop Ghosh, Syedhamidreza Motaman, Jae Won Jang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Due to the ever-increasing threat of Reverse Engineering (RE) of Intellectual Property (IP) for malicious gains, camouflaging of logic gates is becoming very important. In this paper, we present experimental demonstration of transistor threshold voltage-defined switch [2] based camouflaged logic gates that can hide six logic functionalities i.e. NAND, AND, NOR, OR, XOR and XNOR. The proposed gates can be used to design the IP, forcing an adversary to perform brute-force guess-and-verify of the underlying functionality-increasing the RE effort. We propose two flavors of camouflaging, one employing only a pass transistor (NMOS-switch) and the other utilizing a full pass transistor (CMOS-switch). The camouflaged gates are used to design Ring-Oscillators (RO) in ST 65nm technology, one for each functionality, on which we have performed temperature, voltage, and process-variation analysis. We observe that CMOS-switch based camouflaged gate offers a higher performance (∼1.5 - 8X better) than NMOS-switch based gate at an added area cost of only 5%. The proposed gates show functionality till 0.65V. We are also able to reclaim lost performance by dynamically changing the switch gate voltage and show that robust operation can be achieved at lower voltage and under temperature fluctuation.

Original languageEnglish (US)
Title of host publicationISLPED 2018 - Proceedings of the 2018 International Symposium on Low Power Electronics and Design
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781450357043
DOIs
StatePublished - Jul 23 2018
Event23rd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2018 - Bellevue, United States
Duration: Jul 23 2018Jul 25 2018

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Other

Other23rd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2018
CountryUnited States
CityBellevue
Period7/23/187/25/18

Fingerprint

Reverse engineering
Switches
Transistors
Logic gates
Intellectual property
Electric potential
Flavors
Threshold voltage
Demonstrations
Temperature
Costs

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Iyengar, A. S., Vontela, D., Reddy, I., Ghosh, S., Motaman, S., & Jang, J. W. (2018). Threshold defined camouflaged gates in 65nm technology for reverse engineering protection. In ISLPED 2018 - Proceedings of the 2018 International Symposium on Low Power Electronics and Design [a6] (Proceedings of the International Symposium on Low Power Electronics and Design). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/3218603.3218641
Iyengar, Anirudh S. ; Vontela, Deepak ; Reddy, Ithihasa ; Ghosh, Swaroop ; Motaman, Syedhamidreza ; Jang, Jae Won. / Threshold defined camouflaged gates in 65nm technology for reverse engineering protection. ISLPED 2018 - Proceedings of the 2018 International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc., 2018. (Proceedings of the International Symposium on Low Power Electronics and Design).
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abstract = "Due to the ever-increasing threat of Reverse Engineering (RE) of Intellectual Property (IP) for malicious gains, camouflaging of logic gates is becoming very important. In this paper, we present experimental demonstration of transistor threshold voltage-defined switch [2] based camouflaged logic gates that can hide six logic functionalities i.e. NAND, AND, NOR, OR, XOR and XNOR. The proposed gates can be used to design the IP, forcing an adversary to perform brute-force guess-and-verify of the underlying functionality-increasing the RE effort. We propose two flavors of camouflaging, one employing only a pass transistor (NMOS-switch) and the other utilizing a full pass transistor (CMOS-switch). The camouflaged gates are used to design Ring-Oscillators (RO) in ST 65nm technology, one for each functionality, on which we have performed temperature, voltage, and process-variation analysis. We observe that CMOS-switch based camouflaged gate offers a higher performance (∼1.5 - 8X better) than NMOS-switch based gate at an added area cost of only 5{\%}. The proposed gates show functionality till 0.65V. We are also able to reclaim lost performance by dynamically changing the switch gate voltage and show that robust operation can be achieved at lower voltage and under temperature fluctuation.",
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Iyengar, AS, Vontela, D, Reddy, I, Ghosh, S, Motaman, S & Jang, JW 2018, Threshold defined camouflaged gates in 65nm technology for reverse engineering protection. in ISLPED 2018 - Proceedings of the 2018 International Symposium on Low Power Electronics and Design., a6, Proceedings of the International Symposium on Low Power Electronics and Design, Institute of Electrical and Electronics Engineers Inc., 23rd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2018, Bellevue, United States, 7/23/18. https://doi.org/10.1145/3218603.3218641

Threshold defined camouflaged gates in 65nm technology for reverse engineering protection. / Iyengar, Anirudh S.; Vontela, Deepak; Reddy, Ithihasa; Ghosh, Swaroop; Motaman, Syedhamidreza; Jang, Jae Won.

ISLPED 2018 - Proceedings of the 2018 International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc., 2018. a6 (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Iyengar AS, Vontela D, Reddy I, Ghosh S, Motaman S, Jang JW. Threshold defined camouflaged gates in 65nm technology for reverse engineering protection. In ISLPED 2018 - Proceedings of the 2018 International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc. 2018. a6. (Proceedings of the International Symposium on Low Power Electronics and Design). https://doi.org/10.1145/3218603.3218641