Threshold-Defined Logic and Interconnect for Protection against Reverse Engineering

Jae Won Jang, Asmit De, Deepak Vontela, Ithihasa Nirmala, Swaroop Ghosh, Anirudh Iyengar

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Securing the intellectual property (IP) from counterfeiting is an important goal toward trustworthy computing. Camouflaging of logic gates is a well-known technique to prevent an adversary from de-layering the chip and stealing IP. In this paper, we propose threshold voltage modulation to realize 2-input static camouflaged logic that can hide six functionalities. We extend the concept of threshold-voltage defined logic to propose multi-input camouflaged gates capable of hiding six 3-input Boolean functions (NAND, NOR, AOI, OAI, XOR, and XNOR). We also propose interconnect camouflaging technique which hides the original connectivity of nets using a novel threshold-voltage defined pass transistor mux. Since threshold voltages are asserted during fabrication and are difficult to identify during optical reverse engineering (RE)-based techniques, the adversary will be forced to launch a brute-force search. We present a thorough analysis of RE effort and overheads associated with the proposed camouflaging techniques. The proposed methodology is demonstrated using fabricated test-chip in 65 nm technology.

Original languageEnglish (US)
Article number8576591
Pages (from-to)308-320
Number of pages13
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume39
Issue number2
DOIs
StatePublished - Feb 2020

Fingerprint

Reverse engineering
Threshold voltage
Intellectual property
Optical engineering
Boolean functions
Logic gates
Transistors
Modulation
Fabrication

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

Jang, Jae Won ; De, Asmit ; Vontela, Deepak ; Nirmala, Ithihasa ; Ghosh, Swaroop ; Iyengar, Anirudh. / Threshold-Defined Logic and Interconnect for Protection against Reverse Engineering. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2020 ; Vol. 39, No. 2. pp. 308-320.
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Threshold-Defined Logic and Interconnect for Protection against Reverse Engineering. / Jang, Jae Won; De, Asmit; Vontela, Deepak; Nirmala, Ithihasa; Ghosh, Swaroop; Iyengar, Anirudh.

In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 39, No. 2, 8576591, 02.2020, p. 308-320.

Research output: Contribution to journalArticle

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