Threshold Switch Augmented STT MRAM: Design Space Analysis and Device-Circuit Co-Design

Ahmedullah Aziz, Sumeet Kumar Gupta

Research output: Contribution to journalArticle

Abstract

We analyze the augmentation of spin-transfer torque (STT) MRAM with electrically driven selective phase transition of a threshold switch (TS) to enhance the read operation. This paper provides a comprehensive discussion on necessary design considerations for TS augmented (TSA) MRAMs. We deduce constraints for read and write biasing that yields improved read operation of TSA MRAMs. We explain the dependence of read/write performance metrics on read/write biases and the properties (resistance and critical currents for transitions) of the TS. With proper device-circuit optimization, TSA MRAM shows up to 70% larger sense margin, ∼27% higher data stability with ∼40% less power for read operation compared to STT MRAM (in nominal condition). We evaluate the impact of variation on TSA MRAM through Monte Carlo simulations. We report that even with variation induced spread in the distribution of bit-line voltages, TSA MRAM provides ∼ 1.7× larger voltage differential between parallel and antiparallel states. For the write operation, the TSA MRAM consumes ∼10% less average power and demands only ∼5% more write time extension than the STT MRAM to achieve the same level of variation tolerance.

Original languageEnglish (US)
Article number8500346
Pages (from-to)5381-5389
Number of pages9
JournalIEEE Transactions on Electron Devices
Volume65
Issue number12
DOIs
StatePublished - Dec 2018

Fingerprint

Torque
Switches
Networks (circuits)
Critical currents
Electric potential
Phase transitions
Monte Carlo simulation

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Aziz, Ahmedullah ; Gupta, Sumeet Kumar. / Threshold Switch Augmented STT MRAM : Design Space Analysis and Device-Circuit Co-Design. In: IEEE Transactions on Electron Devices. 2018 ; Vol. 65, No. 12. pp. 5381-5389.
@article{c0a3137d9a4342459b0f0726ffd4c5ce,
title = "Threshold Switch Augmented STT MRAM: Design Space Analysis and Device-Circuit Co-Design",
abstract = "We analyze the augmentation of spin-transfer torque (STT) MRAM with electrically driven selective phase transition of a threshold switch (TS) to enhance the read operation. This paper provides a comprehensive discussion on necessary design considerations for TS augmented (TSA) MRAMs. We deduce constraints for read and write biasing that yields improved read operation of TSA MRAMs. We explain the dependence of read/write performance metrics on read/write biases and the properties (resistance and critical currents for transitions) of the TS. With proper device-circuit optimization, TSA MRAM shows up to 70{\%} larger sense margin, ∼27{\%} higher data stability with ∼40{\%} less power for read operation compared to STT MRAM (in nominal condition). We evaluate the impact of variation on TSA MRAM through Monte Carlo simulations. We report that even with variation induced spread in the distribution of bit-line voltages, TSA MRAM provides ∼ 1.7× larger voltage differential between parallel and antiparallel states. For the write operation, the TSA MRAM consumes ∼10{\%} less average power and demands only ∼5{\%} more write time extension than the STT MRAM to achieve the same level of variation tolerance.",
author = "Ahmedullah Aziz and Gupta, {Sumeet Kumar}",
year = "2018",
month = "12",
doi = "10.1109/TED.2018.2873738",
language = "English (US)",
volume = "65",
pages = "5381--5389",
journal = "IEEE Transactions on Electron Devices",
issn = "0018-9383",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "12",

}

Threshold Switch Augmented STT MRAM : Design Space Analysis and Device-Circuit Co-Design. / Aziz, Ahmedullah; Gupta, Sumeet Kumar.

In: IEEE Transactions on Electron Devices, Vol. 65, No. 12, 8500346, 12.2018, p. 5381-5389.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Threshold Switch Augmented STT MRAM

T2 - Design Space Analysis and Device-Circuit Co-Design

AU - Aziz, Ahmedullah

AU - Gupta, Sumeet Kumar

PY - 2018/12

Y1 - 2018/12

N2 - We analyze the augmentation of spin-transfer torque (STT) MRAM with electrically driven selective phase transition of a threshold switch (TS) to enhance the read operation. This paper provides a comprehensive discussion on necessary design considerations for TS augmented (TSA) MRAMs. We deduce constraints for read and write biasing that yields improved read operation of TSA MRAMs. We explain the dependence of read/write performance metrics on read/write biases and the properties (resistance and critical currents for transitions) of the TS. With proper device-circuit optimization, TSA MRAM shows up to 70% larger sense margin, ∼27% higher data stability with ∼40% less power for read operation compared to STT MRAM (in nominal condition). We evaluate the impact of variation on TSA MRAM through Monte Carlo simulations. We report that even with variation induced spread in the distribution of bit-line voltages, TSA MRAM provides ∼ 1.7× larger voltage differential between parallel and antiparallel states. For the write operation, the TSA MRAM consumes ∼10% less average power and demands only ∼5% more write time extension than the STT MRAM to achieve the same level of variation tolerance.

AB - We analyze the augmentation of spin-transfer torque (STT) MRAM with electrically driven selective phase transition of a threshold switch (TS) to enhance the read operation. This paper provides a comprehensive discussion on necessary design considerations for TS augmented (TSA) MRAMs. We deduce constraints for read and write biasing that yields improved read operation of TSA MRAMs. We explain the dependence of read/write performance metrics on read/write biases and the properties (resistance and critical currents for transitions) of the TS. With proper device-circuit optimization, TSA MRAM shows up to 70% larger sense margin, ∼27% higher data stability with ∼40% less power for read operation compared to STT MRAM (in nominal condition). We evaluate the impact of variation on TSA MRAM through Monte Carlo simulations. We report that even with variation induced spread in the distribution of bit-line voltages, TSA MRAM provides ∼ 1.7× larger voltage differential between parallel and antiparallel states. For the write operation, the TSA MRAM consumes ∼10% less average power and demands only ∼5% more write time extension than the STT MRAM to achieve the same level of variation tolerance.

UR - http://www.scopus.com/inward/record.url?scp=85055212989&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85055212989&partnerID=8YFLogxK

U2 - 10.1109/TED.2018.2873738

DO - 10.1109/TED.2018.2873738

M3 - Article

AN - SCOPUS:85055212989

VL - 65

SP - 5381

EP - 5389

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

IS - 12

M1 - 8500346

ER -