Tolerating write disturbance errors in pcm: Experimental characterization, analysis, and mechanisms

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Constant technology scaling has enabled modern computing systems to achieve high degrees of thread-level parallelism, making the design of a highly scalable and dense main memory subsystem a major challenge, especially for data-intensive workloads. While during the past three decades DRAM has been widely used as the dominant technology to build main memory, it faces serious scalability and power consumption problems at sub-micron scales. Phase Change Memory (PCM) has been proposed as one of the most promising technologies to replace DRAM in future computing systems, because of its short access latency and high scalability. However, PCM has some reliability problems below 20nm technology. As the cell size scales down, the thermal-disturbance between the cells is exacerbated. More precisely, the generated heat during the write operation can disseminate to the adjacent cells and potentially change their values. This phenomenon is known as the write disturbance problem. In this work, we study the impact of write disturbance along the word-line and bit-line in a PCM-based main memory. We then propose two low-overhead mechanisms to address this problem in different dimensions. Our proposed schemes are based on a rank subsetting memory architecture where each chip can be accessed separately. To mitigate the write disturbance problem along the word-line, we use a combination of differential write (DW) and verify-And-correct (VnC) schemes only if the chance of having cascaded verification steps is low. Otherwise, we write into all the vulnerable cells within the target chip to avoid performance loss. To tolerate write disturbance along the bit-line, we use data compression to compact the data and place the adjacent memory lines in a non-overlapping fashion. We further use the extra space within a compressed memory line to store BCH code, in order to protect read-intensive memory lines against write-intensive addresses. Our proposed schemes guarantee reliable write operations in a super dense PCM-based main memory, and improve the system performance by 17% on average, compared to the state-of-The-Art mechanism in this domain.

Original languageEnglish (US)
Title of host publicationProceedings - 26th IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, MASCOTS 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages53-65
Number of pages13
ISBN (Electronic)9781538668863
DOIs
StatePublished - Nov 7 2018
Event26th IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, MASCOTS 2018 - Milwaukee, United States
Duration: Sep 25 2018Sep 28 2018

Publication series

NameProceedings - 26th IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, MASCOTS 2018

Other

Other26th IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, MASCOTS 2018
CountryUnited States
CityMilwaukee
Period9/25/189/28/18

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Modeling and Simulation

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    Jadidi, A., Kandemir, M., & Das, C. (2018). Tolerating write disturbance errors in pcm: Experimental characterization, analysis, and mechanisms. In Proceedings - 26th IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, MASCOTS 2018 (pp. 53-65). [8526871] (Proceedings - 26th IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, MASCOTS 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MASCOTS.2018.00013