There has been considerable interest in bottom-up integration of semiconductor nanowires for their application in future logic, memory, and sensor circuits. 1'2 The ability to grow p- and n-type silicon nanowires (SiNWs) of varying carrier density has been demonstrated, 3,4 which is a first step towards fabricating complementary circuits using such technologies. However, the subthreshold properties of SiNW field effect transistors (FETs) often exhibit severe hysteresis due to their large unpassivated surface area. Moreover, the trade-off between high gate modulation and channel injection efficiency still remains a challenge. In this talk, we will present the results of FETs fabricated using thermally-oxidized p -, n -, and p +/p -/p + SiNWs, which show a dramatic improvement in operational stability as compared to unpassivated SiNW FETs. The SiNWs used in these studies were synthesized by vapor-liquid-solid (VLS) growth from Au catalyst particles using 10% SiH 4 in H 2 as the silicon gas source 5, trimethylboron (TMB) as the p-type dopant, and phosphine (PH 3) as the n-type dopant. The ratio of TMB or PH 3 to SiH 4 was varied from 0 to 10 -2 to modulate the hole or electron carrier concentration in the SiNWs. Following growth, the Au catalyst particles were removed from the tips of the as-grown SiNWs, and the wires were cleaned using a modified RCA process prior to dry thermal oxidation at 700°C for 4 hours. Transmission electron microscopy studies show that the interface between the SiNW core and the ∼10 nm thick SiO 2 shell is smooth and uniform. These SiNWs were integrated onto a top- and back-gated test structure by electrofludically aligning individual wires between pairs of large area electrodes. Source and drain (S/D) contacts were defined by first removing the oxide shell at the NW tips and then lifting off Ti(100nm)/Au(60nm) metal. Non-self-aligned 3 μm long top gates comprised of Ti(60nm)/Au(40nm) were then deposited on the SiO 2 shell, which served as the top gate dielectric. The n ++ Si substrate coated with 100 nm of LPCVD Si 3N 4 was used as a back gate in these structures. The breakdown field strength and the interface charge state density estimated from subthreshold measurements is approximately 5×10 6 V/cm and 4×10 12 cm -2eV -1. Significantly less hysteresis in the subthreshold characteristics was observed for different sweep rates and directions in top-gated, thermally-oxidized p - SiNW FETs as compared to back-gated, non-oxidized p - SiNW FETs. This improvement could be due in part to the improved passivation provided by the SiO 2 shell. The top-gated p - SiNW FETs had threshold voltages of ∼1 V and subthreshold slopes of ∼0.25 V/decade, which are consistent with values expected for devices with a 10nm thick SiO 2 gate dielectric. An On/Off ratio of 10 5 was measured when a -10 V back-gate voltage was applied to lower the S/D Schottky barrier and increase the on-state current of the SiNW FET. Under these conditions, the on-state current and the field effect mobility of these devices are ∼10nA@V DS=1V and 10cm 2/Vs, which are both limited by the S/D contacts. For comparison, the n - SiNW FETs showed threshold voltages of ∼-2 V, subthreshold slopes of ∼0.23 V/decade and On/Off ratios of ∼10 5. Additional p - SiNWs were grown by incorporating p + segments at the NW tips to reduce the S/D contact resistance and increase the on-state current. The on-state current and On/Off ratio of these devices at the same back-gate voltage of -10V are approximately one order of magnitude higher than the p - SiNW FETs. These results emphasize that future efforts must be devoted to improving the interfacial properties between SiNW core and the gate dielectric, developing strategies for introducing abrupt intentionally-doped NW segments by VLS, and reproducibly releasing and assembling segmented NWs to fabricate nm-scale self-aligned devices. These enhancements will facilitate an improved understanding of the potential benefits of NW-based field effect devices for future nanoelectronic applications.