Total power optimization through simultaneously multiple-VDD multiple-VTH assignment and device sizing with stack forcing

W. Hung, Y. Xie, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, Y. Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Scopus citations

Abstract

In this paper, we present an algorithm for the minimization of total power consumption via multiple VDD assignment, multiple VTH assignment, device sizing and stack forcing, while maintaining performance requirements. These four power reduction techniques are properly encoded in genetic algorithm and evaluated simultaneously. The overhead imposed by the insertion of level converters is also taken into account. The effectiveness of each power reduction mechanism is verified, as are the combinations of different approaches. Experimental results are given for a number of 65 nm benchmark circuits that span typical circuit topologies, including inverter chains, SRAM decoders, multiplier and a 32bit carry adders. From the experimental results, we show that the combination of four low power techniques is the effective way to achieve low power budget.

Original languageEnglish (US)
Title of host publicationProceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04
PublisherAssociation for Computing Machinery (ACM)
Pages144-149
Number of pages6
ISBN (Print)1581139292, 9781581139297
DOIs
StatePublished - 2004
EventProceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04 - Newport Beach, CA, United States
Duration: Aug 9 2004Aug 11 2004

Publication series

NameProceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04

Other

OtherProceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04
CountryUnited States
CityNewport Beach, CA
Period8/9/048/11/04

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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    Hung, W., Xie, Y., Vijaykrishnan, N., Kandemir, M., Irwin, M. J., & Tsai, Y. (2004). Total power optimization through simultaneously multiple-VDD multiple-VTH assignment and device sizing with stack forcing. In Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04 (pp. 144-149). [5.2] (Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04). Association for Computing Machinery (ACM). https://doi.org/10.1145/1013235.1013276