Total Power Optimization through Simultaneously Multiple-VDD Multiple-VTH Assignment and Device Sizing with Stack Forcing

W. Hung, Y. Xie, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, Y. Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

In this paper, we present an algorithm for the minimization of total power consumption via multiple VDD assignment, multiple VTH assignment, device sizing and stack forcing, while maintaining performance requirements. These four power reduction techniques are properly encoded in genetic algorithm and evaluated simultaneously. The overhead imposed by the insertion of level converters is also taken into account. The effectiveness of each power reduction mechanism is verified, as are the combinations of different approaches. Experimental results are given for a number of 65 nm benchmark circuits that span typical circuit topologies, including inverter chains, SRAM decoders, multiplier and a 32bit carry adders. From the experimental results, we show that the combination of four low power techniques is the effective way to achieve low power budget.

Original languageEnglish (US)
Title of host publicationISLPED 2004 - Proceedings of the 2004 International Symposium on Low Power Electronics and Design
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages144-149
Number of pages6
EditionJanuary
ISBN (Electronic)1581139292, 1581139292
DOIs
StatePublished - Jan 1 2004
Event2004 International Symposium on Low Power Electronics and Design, ISLPED 2004 - Newport Beach, United States
Duration: Aug 9 2004Aug 11 2004

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
NumberJanuary
Volume2004-January
ISSN (Print)1533-4678

Other

Other2004 International Symposium on Low Power Electronics and Design, ISLPED 2004
Country/TerritoryUnited States
CityNewport Beach
Period8/9/048/11/04

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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