Towards energy-aware iteration space tiling

M. Kandemir, N. Vijaykrishnan, M. J. Irwin, H. S. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Iteration space (loop) tiling is a widely used loop-level compiler optimization that can improve performance of array-dominated codes. But, in current designs (in particular in embedded and mobile devices), low energy consumption is becoming as important as performance. Towards understanding the influence of tiling on system energy, in this paper, we investigate energy behavior of tiling.

Original languageEnglish (US)
Title of host publicationLanguages, Compilers and Tools for Embedded Systems - ACM SIGPLAN Workshop LCTES 2000, Proceedings
EditorsJack Davidson, Sang Lyul Min
PublisherSpringer Verlag
Pages211-215
Number of pages5
ISBN (Print)3540417818, 9783540417811
DOIs
StatePublished - 2001
EventACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems, LCTES 2000 - Vancouver, Canada
Duration: Jun 18 2000Jun 18 2000

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume1985
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Other

OtherACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems, LCTES 2000
CountryCanada
CityVancouver
Period6/18/006/18/00

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Computer Science(all)

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  • Cite this

    Kandemir, M., Vijaykrishnan, N., Irwin, M. J., & Kim, H. S. (2001). Towards energy-aware iteration space tiling. In J. Davidson, & S. L. Min (Eds.), Languages, Compilers and Tools for Embedded Systems - ACM SIGPLAN Workshop LCTES 2000, Proceedings (pp. 211-215). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 1985). Springer Verlag. https://doi.org/10.1007/3-540-45245-1_16