Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint

Manjit Borah, Robert Michael Owens, Mary Jane Irwin

Research output: Contribution to conferencePaper

30 Scopus citations

Abstract

We consider the problem of transistor sizing in a static CMOS layout to minimize the power consumption of the circuit subject to a given delay constraint. Based on our characterization of the short circuit power dissipation of a CMOS circuit we show that the transistors of a gate with high fan-out load should be enlarged to minimize the power consumption of the circuit. We derive analytical formulation for computing the power optimal size of a transistor and isolate the factor affecting the power optimal size. We extend our model to analyze power-delay characteristic of a CMOS circuit and derive the power-delay optimal size of a transistor. Based on our model we develop heuristics to perform transistor sizing in CMOS layouts for minimizing power consumption while meeting given delay constraints. Experimental results (SPICE simulations) are presented to confirm the correctness of our analytical model.

Original languageEnglish (US)
Pages167-172
Number of pages6
StatePublished - Jan 1 1995
EventProceedings of the 1995 International Symposium on Low Power Design - Dana Point, CA, USA
Duration: Apr 23 1995Apr 26 1995

Conference

ConferenceProceedings of the 1995 International Symposium on Low Power Design
CityDana Point, CA, USA
Period4/23/954/26/95

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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    Borah, M., Owens, R. M., & Irwin, M. J. (1995). Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint. 167-172. Paper presented at Proceedings of the 1995 International Symposium on Low Power Design, Dana Point, CA, USA, .