Truncated-matrix multipliers with coefficient shifting

Eugene George Walters, III, Michael J. Schulte

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Truncated-matrix multipliers offer significant reductions in area, power, and delay, at the expense of increased computational error. These tradeoffs make them an attractive choice for many signal processing systems such as FIR filters. This paper presents a method for shifting coefficients that significantly reduces the error in systems that use truncated-matrix multipliers. This method allows further reductions in area, power, and delay while maintaining the overall accuracy of the system.

Original languageEnglish (US)
Title of host publicationConference Record of the 45th Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2011
Pages176-180
Number of pages5
DOIs
StatePublished - Dec 1 2011
Event45th Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2011 - Pacific Grove, CA, United States
Duration: Nov 6 2011Nov 9 2011

Publication series

NameConference Record - Asilomar Conference on Signals, Systems and Computers
ISSN (Print)1058-6393

Other

Other45th Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2011
CountryUnited States
CityPacific Grove, CA
Period11/6/1111/9/11

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Networks and Communications

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    Walters, III, E. G., & Schulte, M. J. (2011). Truncated-matrix multipliers with coefficient shifting. In Conference Record of the 45th Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2011 (pp. 176-180). [6189979] (Conference Record - Asilomar Conference on Signals, Systems and Computers). https://doi.org/10.1109/ACSSC.2011.6189979