TS-Router

On maximizing the Quality-of-Allocation in the On-Chip Network

Yuan Ying Chang, Yoshi Shih Chieh Huang, Matthew Poremba, Vijaykrishnan Narayanan, Yuan Xie, Chung Ta King

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Abstract

Switch allocation is a critical pipeline stage in the router of an Network-on-Chip (NoC), in which flits in the input ports of the router are assigned to the output ports for forwarding. This allocation is in essence a matching between the input requests and output port resources. Efficient router designs strive to maximize the matching. Previous research considers the allocation decision at each cycle either independently or depending on prior allocations. In this paper, we demonstrate that the matching decisions made in a router along time actually form a time series, and the Quality-of-Allocation (QoA) can be maximized if the matching decision is made across the time series, from past history to future requests. Based on this observation, a novel router design, TS-Router, is proposed. TS-Router predicts future requests to arrive at a router and tries to maximize the matching across cycles. It can be extended easily from most state-of-the-art routers in a lightweight fashion. Our evaluation of TS-Router uses synthetic traffic as well as real benchmark programs in full-system simulator. The results show that TS-Router can have higher number of matchings and lower latency. In addition, a prototype of TS-Router is implemented in Verilog, so that power consumption and area overhead are also evaluated.

Original languageEnglish (US)
Title of host publication19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013
Pages390-399
Number of pages10
DOIs
StatePublished - Jul 23 2013
Event19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013 - Shenzhen, China
Duration: Feb 23 2013Feb 27 2013

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
ISSN (Print)1530-0897

Other

Other19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013
CountryChina
CityShenzhen
Period2/23/132/27/13

Fingerprint

Routers
Network-on-chip
Time series
Computer hardware description languages
Electric power utilization
Pipelines
Simulators
Switches

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Cite this

Chang, Y. Y., Huang, Y. S. C., Poremba, M., Narayanan, V., Xie, Y., & King, C. T. (2013). TS-Router: On maximizing the Quality-of-Allocation in the On-Chip Network. In 19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013 (pp. 390-399). [6522335] (Proceedings - International Symposium on High-Performance Computer Architecture). https://doi.org/10.1109/HPCA.2013.6522335
Chang, Yuan Ying ; Huang, Yoshi Shih Chieh ; Poremba, Matthew ; Narayanan, Vijaykrishnan ; Xie, Yuan ; King, Chung Ta. / TS-Router : On maximizing the Quality-of-Allocation in the On-Chip Network. 19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013. 2013. pp. 390-399 (Proceedings - International Symposium on High-Performance Computer Architecture).
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abstract = "Switch allocation is a critical pipeline stage in the router of an Network-on-Chip (NoC), in which flits in the input ports of the router are assigned to the output ports for forwarding. This allocation is in essence a matching between the input requests and output port resources. Efficient router designs strive to maximize the matching. Previous research considers the allocation decision at each cycle either independently or depending on prior allocations. In this paper, we demonstrate that the matching decisions made in a router along time actually form a time series, and the Quality-of-Allocation (QoA) can be maximized if the matching decision is made across the time series, from past history to future requests. Based on this observation, a novel router design, TS-Router, is proposed. TS-Router predicts future requests to arrive at a router and tries to maximize the matching across cycles. It can be extended easily from most state-of-the-art routers in a lightweight fashion. Our evaluation of TS-Router uses synthetic traffic as well as real benchmark programs in full-system simulator. The results show that TS-Router can have higher number of matchings and lower latency. In addition, a prototype of TS-Router is implemented in Verilog, so that power consumption and area overhead are also evaluated.",
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Chang, YY, Huang, YSC, Poremba, M, Narayanan, V, Xie, Y & King, CT 2013, TS-Router: On maximizing the Quality-of-Allocation in the On-Chip Network. in 19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013., 6522335, Proceedings - International Symposium on High-Performance Computer Architecture, pp. 390-399, 19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013, Shenzhen, China, 2/23/13. https://doi.org/10.1109/HPCA.2013.6522335

TS-Router : On maximizing the Quality-of-Allocation in the On-Chip Network. / Chang, Yuan Ying; Huang, Yoshi Shih Chieh; Poremba, Matthew; Narayanan, Vijaykrishnan; Xie, Yuan; King, Chung Ta.

19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013. 2013. p. 390-399 6522335 (Proceedings - International Symposium on High-Performance Computer Architecture).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AB - Switch allocation is a critical pipeline stage in the router of an Network-on-Chip (NoC), in which flits in the input ports of the router are assigned to the output ports for forwarding. This allocation is in essence a matching between the input requests and output port resources. Efficient router designs strive to maximize the matching. Previous research considers the allocation decision at each cycle either independently or depending on prior allocations. In this paper, we demonstrate that the matching decisions made in a router along time actually form a time series, and the Quality-of-Allocation (QoA) can be maximized if the matching decision is made across the time series, from past history to future requests. Based on this observation, a novel router design, TS-Router, is proposed. TS-Router predicts future requests to arrive at a router and tries to maximize the matching across cycles. It can be extended easily from most state-of-the-art routers in a lightweight fashion. Our evaluation of TS-Router uses synthetic traffic as well as real benchmark programs in full-system simulator. The results show that TS-Router can have higher number of matchings and lower latency. In addition, a prototype of TS-Router is implemented in Verilog, so that power consumption and area overhead are also evaluated.

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Chang YY, Huang YSC, Poremba M, Narayanan V, Xie Y, King CT. TS-Router: On maximizing the Quality-of-Allocation in the On-Chip Network. In 19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013. 2013. p. 390-399. 6522335. (Proceedings - International Symposium on High-Performance Computer Architecture). https://doi.org/10.1109/HPCA.2013.6522335