Abstract
Switch allocation is a critical pipeline stage in the router of an Network-on-Chip (NoC), in which flits in the input ports of the router are assigned to the output ports for forwarding. This allocation is in essence a matching between the input requests and output port resources. Efficient router designs strive to maximize the matching. Previous research considers the allocation decision at each cycle either independently or depending on prior allocations. In this paper, we demonstrate that the matching decisions made in a router along time actually form a time series, and the Quality-of-Allocation (QoA) can be maximized if the matching decision is made across the time series, from past history to future requests. Based on this observation, a novel router design, TS-Router, is proposed. TS-Router predicts future requests to arrive at a router and tries to maximize the matching across cycles. It can be extended easily from most state-of-the-art routers in a lightweight fashion. Our evaluation of TS-Router uses synthetic traffic as well as real benchmark programs in full-system simulator. The results show that TS-Router can have higher number of matchings and lower latency. In addition, a prototype of TS-Router is implemented in Verilog, so that power consumption and area overhead are also evaluated.
| Original language | English (US) |
|---|---|
| Title of host publication | 19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013 |
| Pages | 390-399 |
| Number of pages | 10 |
| DOIs | |
| State | Published - Jul 23 2013 |
| Event | 19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013 - Shenzhen, China Duration: Feb 23 2013 → Feb 27 2013 |
Publication series
| Name | Proceedings - International Symposium on High-Performance Computer Architecture |
|---|---|
| ISSN (Print) | 1530-0897 |
Other
| Other | 19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013 |
|---|---|
| Country | China |
| City | Shenzhen |
| Period | 2/23/13 → 2/27/13 |
Fingerprint
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
Cite this
}
TS-Router : On maximizing the Quality-of-Allocation in the On-Chip Network. / Chang, Yuan Ying; Huang, Yoshi Shih Chieh; Poremba, Matthew; Narayanan, Vijaykrishnan; Xie, Yuan; King, Chung Ta.
19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013. 2013. p. 390-399 6522335 (Proceedings - International Symposium on High-Performance Computer Architecture).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - TS-Router
T2 - On maximizing the Quality-of-Allocation in the On-Chip Network
AU - Chang, Yuan Ying
AU - Huang, Yoshi Shih Chieh
AU - Poremba, Matthew
AU - Narayanan, Vijaykrishnan
AU - Xie, Yuan
AU - King, Chung Ta
PY - 2013/7/23
Y1 - 2013/7/23
N2 - Switch allocation is a critical pipeline stage in the router of an Network-on-Chip (NoC), in which flits in the input ports of the router are assigned to the output ports for forwarding. This allocation is in essence a matching between the input requests and output port resources. Efficient router designs strive to maximize the matching. Previous research considers the allocation decision at each cycle either independently or depending on prior allocations. In this paper, we demonstrate that the matching decisions made in a router along time actually form a time series, and the Quality-of-Allocation (QoA) can be maximized if the matching decision is made across the time series, from past history to future requests. Based on this observation, a novel router design, TS-Router, is proposed. TS-Router predicts future requests to arrive at a router and tries to maximize the matching across cycles. It can be extended easily from most state-of-the-art routers in a lightweight fashion. Our evaluation of TS-Router uses synthetic traffic as well as real benchmark programs in full-system simulator. The results show that TS-Router can have higher number of matchings and lower latency. In addition, a prototype of TS-Router is implemented in Verilog, so that power consumption and area overhead are also evaluated.
AB - Switch allocation is a critical pipeline stage in the router of an Network-on-Chip (NoC), in which flits in the input ports of the router are assigned to the output ports for forwarding. This allocation is in essence a matching between the input requests and output port resources. Efficient router designs strive to maximize the matching. Previous research considers the allocation decision at each cycle either independently or depending on prior allocations. In this paper, we demonstrate that the matching decisions made in a router along time actually form a time series, and the Quality-of-Allocation (QoA) can be maximized if the matching decision is made across the time series, from past history to future requests. Based on this observation, a novel router design, TS-Router, is proposed. TS-Router predicts future requests to arrive at a router and tries to maximize the matching across cycles. It can be extended easily from most state-of-the-art routers in a lightweight fashion. Our evaluation of TS-Router uses synthetic traffic as well as real benchmark programs in full-system simulator. The results show that TS-Router can have higher number of matchings and lower latency. In addition, a prototype of TS-Router is implemented in Verilog, so that power consumption and area overhead are also evaluated.
UR - http://www.scopus.com/inward/record.url?scp=84880301693&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84880301693&partnerID=8YFLogxK
U2 - 10.1109/HPCA.2013.6522335
DO - 10.1109/HPCA.2013.6522335
M3 - Conference contribution
SN - 9781467355858
T3 - Proceedings - International Symposium on High-Performance Computer Architecture
SP - 390
EP - 399
BT - 19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013
ER -