Tuning data replication for improving behavior of MPSoC applications

O. Ozturk, M. Kandemir, M. J. Irwin, I. Kolcu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Maintaining cache coherence can be very costly for on-chip multiprocessors from an energy perspective. Observing this, we propose a compiler-directed strategy that replicates array data in cache memories of its potential consumer processors at the time the data is brought from off-chip memory. The goal is to eliminate the energy costs associated with bus snooping without negatively impacting overall performance. Our strategy can perform a much better job as compared to static replication strategies, where each array element is replicated based on the same fixed policy.

Original languageEnglish (US)
Title of host publicationProceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004
Subtitle of host publicationVLSI in the Nanometer Era
PublisherAssociation for Computing Machinery (ACM)
Pages170-173
Number of pages4
ISBN (Print)1581138539, 9781581138535
DOIs
StatePublished - Jan 1 2004
EventProceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era - Boston, MA, United States
Duration: Apr 26 2004Apr 28 2004

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI

Other

OtherProceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era
CountryUnited States
CityBoston, MA
Period4/26/044/28/04

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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