Tunnel transistors for energy efficient computing

S. Datta, R. Bijesh, H. Liu, D. Mohata, V. Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

28 Scopus citations

Abstract

Tunnel transistor (TFET) is a potential steep slope device enabling supply voltage scaling. TFET is explored at the device and circuit level. Hetero-junction TFET is demonstrated with high drive current and high on-off current ratio. Hetero-junction TFETs with scaled device geometry can outperform Si FinFET at Vcc<0.3V. Design considerations of TFET based circuits for logic and SRAM applications are investigated and performance benchmarked with Si FinFET technology.

Original languageEnglish (US)
Title of host publication2013 IEEE International Reliability Physics Symposium, IRPS 2013
Pages6A.3.1-6A.3.7
DOIs
StatePublished - Aug 7 2013
Event2013 IEEE International Reliability Physics Symposium, IRPS 2013 - Monterey, CA, United States
Duration: Apr 14 2013Apr 18 2013

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
ISSN (Print)1541-7026

Other

Other2013 IEEE International Reliability Physics Symposium, IRPS 2013
Country/TerritoryUnited States
CityMonterey, CA
Period4/14/134/18/13

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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