Ultra Low energy binary decision diagram circuits using few electron transistors

Vinay Saripalli, Vijay Narayanan, Suman Datta

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Novel medical applications involving embedded sensors, require ultra low energy dissipation with low-to-moderate performance (10kHz-100MHz) driving the conventional MOSFETs into sub-threshold operation regime. In this paper, we present an alternate ultra-low power computing architecture using Binary Decision Diagram based logic circuits implemented using Single Electron Transistors (SETs) operating in the Coulomb blockade regime with very low supply voltages. We evaluate the energy - performance tradeoff metrics of such BDD circuits using time domain Monte Carlo simulations and compare them with the energy-optimized CMOS logic circuits. Simulation results show that the proposed approach achieves better energy-delay characteristics than CMOS realizations.

Original languageEnglish (US)
Title of host publicationNano-Net - 4th International ICST Conference, Nano-Net 2009, Proceedings
Pages200-209
Number of pages10
DOIs
StatePublished - Dec 1 2009
Event4th International ICST Conference on Nano-Net, Nano-Net 2009 - Lucerne, Switzerland
Duration: Oct 18 2009Oct 20 2009

Publication series

NameLecture Notes of the Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering
Volume20 LNICST
ISSN (Print)1867-8211

Other

Other4th International ICST Conference on Nano-Net, Nano-Net 2009
CountrySwitzerland
CityLucerne
Period10/18/0910/20/09

Fingerprint

Binary decision diagrams
Logic circuits
Transistors
Single electron transistors
Coulomb blockade
Electrons
Networks (circuits)
Medical applications
Energy dissipation
Sensors
Electric potential
Monte Carlo simulation

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications

Cite this

Saripalli, V., Narayanan, V., & Datta, S. (2009). Ultra Low energy binary decision diagram circuits using few electron transistors. In Nano-Net - 4th International ICST Conference, Nano-Net 2009, Proceedings (pp. 200-209). (Lecture Notes of the Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering; Vol. 20 LNICST). https://doi.org/10.1007/978-3-642-04850-0_27
Saripalli, Vinay ; Narayanan, Vijay ; Datta, Suman. / Ultra Low energy binary decision diagram circuits using few electron transistors. Nano-Net - 4th International ICST Conference, Nano-Net 2009, Proceedings. 2009. pp. 200-209 (Lecture Notes of the Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering).
@inproceedings{0fd41859e6e8487982d77b7b88ae87fa,
title = "Ultra Low energy binary decision diagram circuits using few electron transistors",
abstract = "Novel medical applications involving embedded sensors, require ultra low energy dissipation with low-to-moderate performance (10kHz-100MHz) driving the conventional MOSFETs into sub-threshold operation regime. In this paper, we present an alternate ultra-low power computing architecture using Binary Decision Diagram based logic circuits implemented using Single Electron Transistors (SETs) operating in the Coulomb blockade regime with very low supply voltages. We evaluate the energy - performance tradeoff metrics of such BDD circuits using time domain Monte Carlo simulations and compare them with the energy-optimized CMOS logic circuits. Simulation results show that the proposed approach achieves better energy-delay characteristics than CMOS realizations.",
author = "Vinay Saripalli and Vijay Narayanan and Suman Datta",
year = "2009",
month = "12",
day = "1",
doi = "10.1007/978-3-642-04850-0_27",
language = "English (US)",
isbn = "3642048498",
series = "Lecture Notes of the Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering",
pages = "200--209",
booktitle = "Nano-Net - 4th International ICST Conference, Nano-Net 2009, Proceedings",

}

Saripalli, V, Narayanan, V & Datta, S 2009, Ultra Low energy binary decision diagram circuits using few electron transistors. in Nano-Net - 4th International ICST Conference, Nano-Net 2009, Proceedings. Lecture Notes of the Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering, vol. 20 LNICST, pp. 200-209, 4th International ICST Conference on Nano-Net, Nano-Net 2009, Lucerne, Switzerland, 10/18/09. https://doi.org/10.1007/978-3-642-04850-0_27

Ultra Low energy binary decision diagram circuits using few electron transistors. / Saripalli, Vinay; Narayanan, Vijay; Datta, Suman.

Nano-Net - 4th International ICST Conference, Nano-Net 2009, Proceedings. 2009. p. 200-209 (Lecture Notes of the Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering; Vol. 20 LNICST).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Ultra Low energy binary decision diagram circuits using few electron transistors

AU - Saripalli, Vinay

AU - Narayanan, Vijay

AU - Datta, Suman

PY - 2009/12/1

Y1 - 2009/12/1

N2 - Novel medical applications involving embedded sensors, require ultra low energy dissipation with low-to-moderate performance (10kHz-100MHz) driving the conventional MOSFETs into sub-threshold operation regime. In this paper, we present an alternate ultra-low power computing architecture using Binary Decision Diagram based logic circuits implemented using Single Electron Transistors (SETs) operating in the Coulomb blockade regime with very low supply voltages. We evaluate the energy - performance tradeoff metrics of such BDD circuits using time domain Monte Carlo simulations and compare them with the energy-optimized CMOS logic circuits. Simulation results show that the proposed approach achieves better energy-delay characteristics than CMOS realizations.

AB - Novel medical applications involving embedded sensors, require ultra low energy dissipation with low-to-moderate performance (10kHz-100MHz) driving the conventional MOSFETs into sub-threshold operation regime. In this paper, we present an alternate ultra-low power computing architecture using Binary Decision Diagram based logic circuits implemented using Single Electron Transistors (SETs) operating in the Coulomb blockade regime with very low supply voltages. We evaluate the energy - performance tradeoff metrics of such BDD circuits using time domain Monte Carlo simulations and compare them with the energy-optimized CMOS logic circuits. Simulation results show that the proposed approach achieves better energy-delay characteristics than CMOS realizations.

UR - http://www.scopus.com/inward/record.url?scp=78649987325&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=78649987325&partnerID=8YFLogxK

U2 - 10.1007/978-3-642-04850-0_27

DO - 10.1007/978-3-642-04850-0_27

M3 - Conference contribution

AN - SCOPUS:78649987325

SN - 3642048498

SN - 9783642048494

T3 - Lecture Notes of the Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering

SP - 200

EP - 209

BT - Nano-Net - 4th International ICST Conference, Nano-Net 2009, Proceedings

ER -

Saripalli V, Narayanan V, Datta S. Ultra Low energy binary decision diagram circuits using few electron transistors. In Nano-Net - 4th International ICST Conference, Nano-Net 2009, Proceedings. 2009. p. 200-209. (Lecture Notes of the Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering). https://doi.org/10.1007/978-3-642-04850-0_27