Ultra-Low Power 3D NC-FinFET-based Monolithic 3D + -IC with Computing-in-Memory for Intelligent IoT Devices

Fu Kuo Hsueh, Wei Hao Chen, Kai Shin Li, Chang Hong Shen, Jia Min Shieh, Chun Ying Lee, Bo Yuan Chen, Hsiu Chih Chen, Chih Chao Yang, Wen Hsien Huang, Kun Ming Chen, Guo Wei Huang, Peng Chen, Yung Ning Tu, Srivatsa Srinivasa, Vijaykrishnan Narayanan, Meng Fan Chang, Wen Kuan Yeh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

For the first time, ultra-low power ferroelectric FinFET-based monolithic 3D + -IC technology was demonstrated for near memory computing (NMC) circuit. Key enablers are ICP-SiO 2 interfacial layer, doped hafnia ferroelectric gate dielectric layer (HfZrO 2 ), and far-infrared laser activation. The proposed stackable 3D NC-FinFETs thus fabricated exhibit record-low sub-threshold swing (NC-nFinFET: 45mV/dec and NC-pFinFET: 50mV/dec) and high I on /I off (>10 6 ) that enable ultra-low power operation ( V DD=100 mV) of CMOS inverter and SRAM. Moreover, above mentioned features of NC-FinFETs and the differential output of SRAM readout enable 50+% area reduction in the near-memory computing circuitry.

Original languageEnglish (US)
Title of host publication2018 IEEE International Electron Devices Meeting, IEDM 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages15.1.1-15.1.4
ISBN (Electronic)9781728119878
DOIs
StatePublished - Jan 16 2019
Event64th Annual IEEE International Electron Devices Meeting, IEDM 2018 - San Francisco, United States
Duration: Dec 1 2018Dec 5 2018

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
Volume2018-December
ISSN (Print)0163-1918

Conference

Conference64th Annual IEEE International Electron Devices Meeting, IEDM 2018
CountryUnited States
CitySan Francisco
Period12/1/1812/5/18

Fingerprint

Static random access storage
Data storage equipment
Ferroelectric materials
infrared lasers
readout
CMOS
Infrared lasers
Gate dielectrics
activation
thresholds
output
Chemical activation
Networks (circuits)
FinFET
Internet of things

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

Cite this

Hsueh, F. K., Chen, W. H., Li, K. S., Shen, C. H., Shieh, J. M., Lee, C. Y., ... Yeh, W. K. (2019). Ultra-Low Power 3D NC-FinFET-based Monolithic 3D + -IC with Computing-in-Memory for Intelligent IoT Devices In 2018 IEEE International Electron Devices Meeting, IEDM 2018 (pp. 15.1.1-15.1.4). [8614697] (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2018-December). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2018.8614697
Hsueh, Fu Kuo ; Chen, Wei Hao ; Li, Kai Shin ; Shen, Chang Hong ; Shieh, Jia Min ; Lee, Chun Ying ; Chen, Bo Yuan ; Chen, Hsiu Chih ; Yang, Chih Chao ; Huang, Wen Hsien ; Chen, Kun Ming ; Huang, Guo Wei ; Chen, Peng ; Tu, Yung Ning ; Srinivasa, Srivatsa ; Narayanan, Vijaykrishnan ; Chang, Meng Fan ; Yeh, Wen Kuan. / Ultra-Low Power 3D NC-FinFET-based Monolithic 3D + -IC with Computing-in-Memory for Intelligent IoT Devices 2018 IEEE International Electron Devices Meeting, IEDM 2018. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 15.1.1-15.1.4 (Technical Digest - International Electron Devices Meeting, IEDM).
@inproceedings{7a9803da8c3641be8388c389e5958ef8,
title = "Ultra-Low Power 3D NC-FinFET-based Monolithic 3D + -IC with Computing-in-Memory for Intelligent IoT Devices",
abstract = "For the first time, ultra-low power ferroelectric FinFET-based monolithic 3D + -IC technology was demonstrated for near memory computing (NMC) circuit. Key enablers are ICP-SiO 2 interfacial layer, doped hafnia ferroelectric gate dielectric layer (HfZrO 2 ), and far-infrared laser activation. The proposed stackable 3D NC-FinFETs thus fabricated exhibit record-low sub-threshold swing (NC-nFinFET: 45mV/dec and NC-pFinFET: 50mV/dec) and high I on /I off (>10 6 ) that enable ultra-low power operation ( V DD=100 mV) of CMOS inverter and SRAM. Moreover, above mentioned features of NC-FinFETs and the differential output of SRAM readout enable 50+{\%} area reduction in the near-memory computing circuitry.",
author = "Hsueh, {Fu Kuo} and Chen, {Wei Hao} and Li, {Kai Shin} and Shen, {Chang Hong} and Shieh, {Jia Min} and Lee, {Chun Ying} and Chen, {Bo Yuan} and Chen, {Hsiu Chih} and Yang, {Chih Chao} and Huang, {Wen Hsien} and Chen, {Kun Ming} and Huang, {Guo Wei} and Peng Chen and Tu, {Yung Ning} and Srivatsa Srinivasa and Vijaykrishnan Narayanan and Chang, {Meng Fan} and Yeh, {Wen Kuan}",
year = "2019",
month = "1",
day = "16",
doi = "10.1109/IEDM.2018.8614697",
language = "English (US)",
series = "Technical Digest - International Electron Devices Meeting, IEDM",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "15.1.1--15.1.4",
booktitle = "2018 IEEE International Electron Devices Meeting, IEDM 2018",
address = "United States",

}

Hsueh, FK, Chen, WH, Li, KS, Shen, CH, Shieh, JM, Lee, CY, Chen, BY, Chen, HC, Yang, CC, Huang, WH, Chen, KM, Huang, GW, Chen, P, Tu, YN, Srinivasa, S, Narayanan, V, Chang, MF & Yeh, WK 2019, Ultra-Low Power 3D NC-FinFET-based Monolithic 3D + -IC with Computing-in-Memory for Intelligent IoT Devices in 2018 IEEE International Electron Devices Meeting, IEDM 2018., 8614697, Technical Digest - International Electron Devices Meeting, IEDM, vol. 2018-December, Institute of Electrical and Electronics Engineers Inc., pp. 15.1.1-15.1.4, 64th Annual IEEE International Electron Devices Meeting, IEDM 2018, San Francisco, United States, 12/1/18. https://doi.org/10.1109/IEDM.2018.8614697

Ultra-Low Power 3D NC-FinFET-based Monolithic 3D + -IC with Computing-in-Memory for Intelligent IoT Devices . / Hsueh, Fu Kuo; Chen, Wei Hao; Li, Kai Shin; Shen, Chang Hong; Shieh, Jia Min; Lee, Chun Ying; Chen, Bo Yuan; Chen, Hsiu Chih; Yang, Chih Chao; Huang, Wen Hsien; Chen, Kun Ming; Huang, Guo Wei; Chen, Peng; Tu, Yung Ning; Srinivasa, Srivatsa; Narayanan, Vijaykrishnan; Chang, Meng Fan; Yeh, Wen Kuan.

2018 IEEE International Electron Devices Meeting, IEDM 2018. Institute of Electrical and Electronics Engineers Inc., 2019. p. 15.1.1-15.1.4 8614697 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2018-December).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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T1 - Ultra-Low Power 3D NC-FinFET-based Monolithic 3D + -IC with Computing-in-Memory for Intelligent IoT Devices

AU - Hsueh, Fu Kuo

AU - Chen, Wei Hao

AU - Li, Kai Shin

AU - Shen, Chang Hong

AU - Shieh, Jia Min

AU - Lee, Chun Ying

AU - Chen, Bo Yuan

AU - Chen, Hsiu Chih

AU - Yang, Chih Chao

AU - Huang, Wen Hsien

AU - Chen, Kun Ming

AU - Huang, Guo Wei

AU - Chen, Peng

AU - Tu, Yung Ning

AU - Srinivasa, Srivatsa

AU - Narayanan, Vijaykrishnan

AU - Chang, Meng Fan

AU - Yeh, Wen Kuan

PY - 2019/1/16

Y1 - 2019/1/16

N2 - For the first time, ultra-low power ferroelectric FinFET-based monolithic 3D + -IC technology was demonstrated for near memory computing (NMC) circuit. Key enablers are ICP-SiO 2 interfacial layer, doped hafnia ferroelectric gate dielectric layer (HfZrO 2 ), and far-infrared laser activation. The proposed stackable 3D NC-FinFETs thus fabricated exhibit record-low sub-threshold swing (NC-nFinFET: 45mV/dec and NC-pFinFET: 50mV/dec) and high I on /I off (>10 6 ) that enable ultra-low power operation ( V DD=100 mV) of CMOS inverter and SRAM. Moreover, above mentioned features of NC-FinFETs and the differential output of SRAM readout enable 50+% area reduction in the near-memory computing circuitry.

AB - For the first time, ultra-low power ferroelectric FinFET-based monolithic 3D + -IC technology was demonstrated for near memory computing (NMC) circuit. Key enablers are ICP-SiO 2 interfacial layer, doped hafnia ferroelectric gate dielectric layer (HfZrO 2 ), and far-infrared laser activation. The proposed stackable 3D NC-FinFETs thus fabricated exhibit record-low sub-threshold swing (NC-nFinFET: 45mV/dec and NC-pFinFET: 50mV/dec) and high I on /I off (>10 6 ) that enable ultra-low power operation ( V DD=100 mV) of CMOS inverter and SRAM. Moreover, above mentioned features of NC-FinFETs and the differential output of SRAM readout enable 50+% area reduction in the near-memory computing circuitry.

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U2 - 10.1109/IEDM.2018.8614697

DO - 10.1109/IEDM.2018.8614697

M3 - Conference contribution

AN - SCOPUS:85061826696

T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 15.1.1-15.1.4

BT - 2018 IEEE International Electron Devices Meeting, IEDM 2018

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Hsueh FK, Chen WH, Li KS, Shen CH, Shieh JM, Lee CY et al. Ultra-Low Power 3D NC-FinFET-based Monolithic 3D + -IC with Computing-in-Memory for Intelligent IoT Devices In 2018 IEEE International Electron Devices Meeting, IEDM 2018. Institute of Electrical and Electronics Engineers Inc. 2019. p. 15.1.1-15.1.4. 8614697. (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2018.8614697