Ultra low power circuit design using tunnel FETs

Ravindhiran Mukundrajan, Matthew Cotter, Vinay Saripalli, Mary Jane Irwin, Suman Datta, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

25 Scopus citations

Abstract

The proliferation of ubiquitous and mobile computing systems has created a new segment in the design space where energy efficiency is the most critical design parameter. With the end user expecting more functionality from these types of systems, there is a pressing need to evaluate emerging technologies that can overcome the limitations of CMOS. This work evaluates the potential of one such prospective MOSFET replacement device - the Tunnel FET (TFET). Novel circuit designs are presented to overcome unique design challenges posed by TFETs. The impacts of the proposed design techniques are characterized and a sparse prefix tree adder employing the proposed designs is presented. A considerable improvement in delay and significant reduction in energy is observed due to the combined impact of circuit and technology co-exploration.

Original languageEnglish (US)
Title of host publicationProceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012
Pages153-158
Number of pages6
DOIs
StatePublished - 2012
Event2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012 - Amherst, MA, United States
Duration: Aug 19 2012Aug 21 2012

Publication series

NameProceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012

Other

Other2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012
Country/TerritoryUnited States
CityAmherst, MA
Period8/19/128/21/12

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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