Using dynamic branch behavior for power-efficient instruction fetch

J. S. Hu, Vijaykrishnan Narayanan, Mary Jane Irwin, Mahmut Kandemir

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Citations (Scopus)

Abstract

Power consumption has become an increasing concern in high performance microprocessor design in terms of packaging and cooling cost. The fetch unit including instruction cache contributes a large portion of the total power consumption in the microprocessor The instruction cache itself suffers some hidden power consumption due to dynamic control flows. Although capturing the dynamic control flows to boost performance, conventional trace caches (CTC) may increase power consumption in the fetch unit due to its simultaneous access to both the trace cache and the instruction cache. By avoiding this simultaneous accesses, sequential trace caches (STC) achieve lower power consumption, but suffer a significant performance loss at the meantime. In this paper we propose dynamic direction prediction based trace cache (DPTC) which avoids simultaneous accesses to the trace cache and the instruction cache with the guide of fetch direction prediction. Experimental results show that dynamic prediction based trace cache can achieve 38.5% power reduction over conventional trace caches and an additional 7.2% reduction over STC, on average, while only trading a 1.8% performance loss compared to CTC.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE Computer Society Annual Symposium on VLSI
Subtitle of host publicationNew Trends and Technologies for VLSI Systems Design, ISVLSI 2003
EditorsNagarajan Ranganathan, Asim Smailagic
PublisherIEEE Computer Society
Pages127-132
Number of pages6
ISBN (Electronic)0769519040
DOIs
StatePublished - Jan 1 2003
EventIEEE Computer Society Annual Symposium on VLSI, ISVLSI 2003 - Tampa, United States
Duration: Feb 20 2003Feb 21 2003

Publication series

NameProceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume2003-January
ISSN (Print)2159-3469
ISSN (Electronic)2159-3477

Other

OtherIEEE Computer Society Annual Symposium on VLSI, ISVLSI 2003
CountryUnited States
CityTampa
Period2/20/032/21/03

Fingerprint

Electric power utilization
Flow control
Microprocessor chips
Packaging
Cooling
Costs

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Hu, J. S., Narayanan, V., Irwin, M. J., & Kandemir, M. (2003). Using dynamic branch behavior for power-efficient instruction fetch. In N. Ranganathan, & A. Smailagic (Eds.), Proceedings - IEEE Computer Society Annual Symposium on VLSI: New Trends and Technologies for VLSI Systems Design, ISVLSI 2003 (pp. 127-132). [1183363] (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2003-January). IEEE Computer Society. https://doi.org/10.1109/ISVLSI.2003.1183363
Hu, J. S. ; Narayanan, Vijaykrishnan ; Irwin, Mary Jane ; Kandemir, Mahmut. / Using dynamic branch behavior for power-efficient instruction fetch. Proceedings - IEEE Computer Society Annual Symposium on VLSI: New Trends and Technologies for VLSI Systems Design, ISVLSI 2003. editor / Nagarajan Ranganathan ; Asim Smailagic. IEEE Computer Society, 2003. pp. 127-132 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI).
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Hu, JS, Narayanan, V, Irwin, MJ & Kandemir, M 2003, Using dynamic branch behavior for power-efficient instruction fetch. in N Ranganathan & A Smailagic (eds), Proceedings - IEEE Computer Society Annual Symposium on VLSI: New Trends and Technologies for VLSI Systems Design, ISVLSI 2003., 1183363, Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, vol. 2003-January, IEEE Computer Society, pp. 127-132, IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2003, Tampa, United States, 2/20/03. https://doi.org/10.1109/ISVLSI.2003.1183363

Using dynamic branch behavior for power-efficient instruction fetch. / Hu, J. S.; Narayanan, Vijaykrishnan; Irwin, Mary Jane; Kandemir, Mahmut.

Proceedings - IEEE Computer Society Annual Symposium on VLSI: New Trends and Technologies for VLSI Systems Design, ISVLSI 2003. ed. / Nagarajan Ranganathan; Asim Smailagic. IEEE Computer Society, 2003. p. 127-132 1183363 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2003-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Hu JS, Narayanan V, Irwin MJ, Kandemir M. Using dynamic branch behavior for power-efficient instruction fetch. In Ranganathan N, Smailagic A, editors, Proceedings - IEEE Computer Society Annual Symposium on VLSI: New Trends and Technologies for VLSI Systems Design, ISVLSI 2003. IEEE Computer Society. 2003. p. 127-132. 1183363. (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI). https://doi.org/10.1109/ISVLSI.2003.1183363