TY - GEN
T1 - Using multiple-input NEMS for parallel A/D conversion and image processing
AU - Ma, Kaisheng
AU - Chandramoorthy, Nandhini
AU - Li, Xueqing
AU - Gupta, Sumeet Kumar
AU - Sampson, John
AU - Xie, Yuan
AU - Narayanan, Vijaykrishnan
PY - 2015/10/27
Y1 - 2015/10/27
N2 - The technology advancements in semiconductor process have led to rapid progress in design and fabrication of multiple-input Nano-electro-mechanical relays/switches (NEM relays/NEMS). This work explores the design space of implementing image processing algorithms using a hybrid multiple-input NEMS - CMOS architecture. Different from the existing the approaches of building logic gates (e.g. INV, AND, OR, NAND, NOR, etc.) as conventional CMOS circuits, using NEMS, this work takes advantages of the electrical and mechanical physical features of the NEM relays to implement image processing algorithms. Simulation results show that the multiple-input NEM relays can be applied for decision-making and compare-select image processing algorithms. Moreover, we show that NEM relays can operate as parallel analog-to-digital converters (ADCs) with advantages of leakage reduction and power efficiency.
AB - The technology advancements in semiconductor process have led to rapid progress in design and fabrication of multiple-input Nano-electro-mechanical relays/switches (NEM relays/NEMS). This work explores the design space of implementing image processing algorithms using a hybrid multiple-input NEMS - CMOS architecture. Different from the existing the approaches of building logic gates (e.g. INV, AND, OR, NAND, NOR, etc.) as conventional CMOS circuits, using NEMS, this work takes advantages of the electrical and mechanical physical features of the NEM relays to implement image processing algorithms. Simulation results show that the multiple-input NEM relays can be applied for decision-making and compare-select image processing algorithms. Moreover, we show that NEM relays can operate as parallel analog-to-digital converters (ADCs) with advantages of leakage reduction and power efficiency.
UR - http://www.scopus.com/inward/record.url?scp=84957012585&partnerID=8YFLogxK
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U2 - 10.1109/ISVLSI.2015.114
DO - 10.1109/ISVLSI.2015.114
M3 - Conference contribution
AN - SCOPUS:84957012585
T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
SP - 339
EP - 344
BT - Proceedings - IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015
PB - IEEE Computer Society
T2 - IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015
Y2 - 8 July 2015 through 10 July 2015
ER -