Utilizing self-assembled multilayers in lithographic processing for nanostructure fabrication

Initial evaluation of the electrical integrity of nanogaps

M. E. Anderson, Charan Srinivasan, Raviprakesh Jayaraman, P. S. Weiss, Mark William Horn

Research output: Contribution to journalConference article

12 Citations (Scopus)

Abstract

We apply self-assembly to form multilayers on gold structures formed by lithographic techniques to create patterns with spacings in the 10-100 nm regime. Controlled placement and thickness of these multilayers form "molecular ruler" resists to tailor spacings accurately between lithographically defined structures. We report on recent results both in designing and patterning complex nanostructures by combining photolithography and molecular rulers. After exposure, development, metal deposition, and lift-off of both the photoresist and molecular resist, the final product has secondary structures and gaps selectively oriented to create hierarchical nanostructures. The electrical integrity of the nanogaps formed using this process is evaluated for a variety of multilayer thicknesses and electrodes widths.

Original languageEnglish (US)
Pages (from-to)248-252
Number of pages5
JournalMicroelectronic Engineering
Volume78-79
Issue number1-4
DOIs
StatePublished - Mar 1 2005
EventProceedings of the 30th International Conference on Micro- and Nano-Engineering -
Duration: Sep 19 2004Sep 22 2004

Fingerprint

nanofabrication
integrity
Nanostructures
Multilayers
spacing
Fabrication
evaluation
photolithography
Processing
photoresists
self assembly
Photolithography
Photoresists
gold
Gold
Self assembly
electrodes
products
Metals
metals

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering

Cite this

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Utilizing self-assembled multilayers in lithographic processing for nanostructure fabrication : Initial evaluation of the electrical integrity of nanogaps. / Anderson, M. E.; Srinivasan, Charan; Jayaraman, Raviprakesh; Weiss, P. S.; Horn, Mark William.

In: Microelectronic Engineering, Vol. 78-79, No. 1-4, 01.03.2005, p. 248-252.

Research output: Contribution to journalConference article

TY - JOUR

T1 - Utilizing self-assembled multilayers in lithographic processing for nanostructure fabrication

T2 - Initial evaluation of the electrical integrity of nanogaps

AU - Anderson, M. E.

AU - Srinivasan, Charan

AU - Jayaraman, Raviprakesh

AU - Weiss, P. S.

AU - Horn, Mark William

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