Validation of an architectural level power analysis technique

Rita Yu Chen, Robert M. Owens, Mary Jane Irwin, Raminder S. Bajwa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Scopus citations

Abstract

This paper presents a technique used to do power analysis of a real processor at the architectural level. The target processor integrates a 16-bit DSP and a 32-bit RISC on a single chip. Our power estimator provides power consumption data of the architecture based on the instructional data flow stream. We demonstrate the accuracy of the estimator by comparing the power values it produces against measurements made by a gate level power simulator for the same benchmark set. Our estimation approach has been shown to provide very efficient, accurate power analysis at the architectural level.

Original languageEnglish (US)
Title of host publicationProceedings 1998 - Design and Automation Conference, DAC 1998
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages242-245
Number of pages4
ISBN (Print)078034409X
StatePublished - Jan 1 1998
Event35th Design and Automation Conference, DAC 1998 - San Francisco, United States
Duration: Jun 15 1998Jun 19 1998

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Other

Other35th Design and Automation Conference, DAC 1998
CountryUnited States
CitySan Francisco
Period6/15/986/19/98

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation
  • Hardware and Architecture

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    Chen, R. Y., Owens, R. M., Irwin, M. J., & Bajwa, R. S. (1998). Validation of an architectural level power analysis technique. In Proceedings 1998 - Design and Automation Conference, DAC 1998 (pp. 242-245). [724474] (Proceedings - Design Automation Conference). Institute of Electrical and Electronics Engineers Inc..