Validation of an architectural level power analysis technique

Rita Yu Chen, Robert M. Owens, Mary Jane Irwin, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

20 Citations (Scopus)

Abstract

This paper presents a technique used to do power analysis of a real processor at the architectural level. The target processor integrates a 16-bit DSP and a 32-bit RISC on a single chip. Our power estimator provides power consumption data of the architecture based on the instructional data flow stream. We demonstrate the accuracy of the estimator by comparing the power values it produces against measurements made by a gate level power simulator for the same benchmark set. Our estimation approach has been shown to provide very efficient, accurate power analysis at the architectural level.

Original languageEnglish (US)
Title of host publicationProceedings 1998 - Design and Automation Conference, DAC 1998
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages242-245
Number of pages4
ISBN (Print)078034409X
StatePublished - Jan 1 1998
Event35th Design and Automation Conference, DAC 1998 - San Francisco, United States
Duration: Jun 15 1998Jun 19 1998

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Other

Other35th Design and Automation Conference, DAC 1998
CountryUnited States
CitySan Francisco
Period6/15/986/19/98

Fingerprint

Power Analysis
Reduced instruction set computing
Estimator
Electric power utilization
Simulators
Data Flow
Power Consumption
Simulator
Chip
Integrate
Benchmark
Target
Demonstrate
Architecture

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation
  • Hardware and Architecture

Cite this

Chen, R. Y., Owens, R. M., Irwin, M. J., & Irwin, M. J. (1998). Validation of an architectural level power analysis technique. In Proceedings 1998 - Design and Automation Conference, DAC 1998 (pp. 242-245). [724474] (Proceedings - Design Automation Conference). Institute of Electrical and Electronics Engineers Inc..
Chen, Rita Yu ; Owens, Robert M. ; Irwin, Mary Jane ; Irwin, Mary Jane. / Validation of an architectural level power analysis technique. Proceedings 1998 - Design and Automation Conference, DAC 1998. Institute of Electrical and Electronics Engineers Inc., 1998. pp. 242-245 (Proceedings - Design Automation Conference).
@inproceedings{8202cd97b5ef4c9e990b6341e4e20e46,
title = "Validation of an architectural level power analysis technique",
abstract = "This paper presents a technique used to do power analysis of a real processor at the architectural level. The target processor integrates a 16-bit DSP and a 32-bit RISC on a single chip. Our power estimator provides power consumption data of the architecture based on the instructional data flow stream. We demonstrate the accuracy of the estimator by comparing the power values it produces against measurements made by a gate level power simulator for the same benchmark set. Our estimation approach has been shown to provide very efficient, accurate power analysis at the architectural level.",
author = "Chen, {Rita Yu} and Owens, {Robert M.} and Irwin, {Mary Jane} and Irwin, {Mary Jane}",
year = "1998",
month = "1",
day = "1",
language = "English (US)",
isbn = "078034409X",
series = "Proceedings - Design Automation Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "242--245",
booktitle = "Proceedings 1998 - Design and Automation Conference, DAC 1998",
address = "United States",

}

Chen, RY, Owens, RM, Irwin, MJ & Irwin, MJ 1998, Validation of an architectural level power analysis technique. in Proceedings 1998 - Design and Automation Conference, DAC 1998., 724474, Proceedings - Design Automation Conference, Institute of Electrical and Electronics Engineers Inc., pp. 242-245, 35th Design and Automation Conference, DAC 1998, San Francisco, United States, 6/15/98.

Validation of an architectural level power analysis technique. / Chen, Rita Yu; Owens, Robert M.; Irwin, Mary Jane; Irwin, Mary Jane.

Proceedings 1998 - Design and Automation Conference, DAC 1998. Institute of Electrical and Electronics Engineers Inc., 1998. p. 242-245 724474 (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Validation of an architectural level power analysis technique

AU - Chen, Rita Yu

AU - Owens, Robert M.

AU - Irwin, Mary Jane

AU - Irwin, Mary Jane

PY - 1998/1/1

Y1 - 1998/1/1

N2 - This paper presents a technique used to do power analysis of a real processor at the architectural level. The target processor integrates a 16-bit DSP and a 32-bit RISC on a single chip. Our power estimator provides power consumption data of the architecture based on the instructional data flow stream. We demonstrate the accuracy of the estimator by comparing the power values it produces against measurements made by a gate level power simulator for the same benchmark set. Our estimation approach has been shown to provide very efficient, accurate power analysis at the architectural level.

AB - This paper presents a technique used to do power analysis of a real processor at the architectural level. The target processor integrates a 16-bit DSP and a 32-bit RISC on a single chip. Our power estimator provides power consumption data of the architecture based on the instructional data flow stream. We demonstrate the accuracy of the estimator by comparing the power values it produces against measurements made by a gate level power simulator for the same benchmark set. Our estimation approach has been shown to provide very efficient, accurate power analysis at the architectural level.

UR - http://www.scopus.com/inward/record.url?scp=0031624028&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0031624028&partnerID=8YFLogxK

M3 - Conference contribution

SN - 078034409X

T3 - Proceedings - Design Automation Conference

SP - 242

EP - 245

BT - Proceedings 1998 - Design and Automation Conference, DAC 1998

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Chen RY, Owens RM, Irwin MJ, Irwin MJ. Validation of an architectural level power analysis technique. In Proceedings 1998 - Design and Automation Conference, DAC 1998. Institute of Electrical and Electronics Engineers Inc. 1998. p. 242-245. 724474. (Proceedings - Design Automation Conference).