Variation-aware low-power buffer design

Chrysostomos Nicopoulos, Aditya Yanamandra, Suresh Srinivasan, N. Vijaykrishnan, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

Process Variation (PV) is a consequence of manufacturing imperfections, which may lead to degraded performance or higher leakage power. In this paper, we focus on the design of an intelligent buffer that logically reorders the entries in FIFO buffer to minimize overall leakage power consumption. The buffer architecture, called IntelliBuffer, has been designed and evaluated in 90 nm and 32 nm CMOS technology. Our synthesized results show that our proposed design is as fast as a conventional buffer structure, while providing the ability to reduce power consumption significantly. When our buffer was used in a Network-on-Chip (NoC) implementation, we obtained 24% leakage savings at 90 nm, and savings of 28% at 32 nm. To further validate the efficacy of our proposed design, we incorporated IntelliBuffer into ViChaR, a recently introduced dynamic buffer management system for NoC routers. Experimental results indicate a marked reduction in ViChaR's leakage power consumption (21% at 90 nm) when IntelliBuffer is employed.

Original languageEnglish (US)
Title of host publicationConference Record of the 41st Asilomar Conference on Signals, Systems and Computers, ACSSC
Pages1402-1406
Number of pages5
DOIs
StatePublished - Dec 1 2007
Event41st Asilomar Conference on Signals, Systems and Computers, ACSSC - Pacific Grove, CA, United States
Duration: Nov 4 2007Nov 7 2007

Publication series

NameConference Record - Asilomar Conference on Signals, Systems and Computers
ISSN (Print)1058-6393

Other

Other41st Asilomar Conference on Signals, Systems and Computers, ACSSC
CountryUnited States
CityPacific Grove, CA
Period11/4/0711/7/07

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Networks and Communications

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