TY - GEN
T1 - Variation-aware low-power buffer design
AU - Nicopoulos, Chrysostomos
AU - Yanamandra, Aditya
AU - Srinivasan, Suresh
AU - Vijaykrishnan, N.
AU - Irwin, Mary Jane
PY - 2007/12/1
Y1 - 2007/12/1
N2 - Process Variation (PV) is a consequence of manufacturing imperfections, which may lead to degraded performance or higher leakage power. In this paper, we focus on the design of an intelligent buffer that logically reorders the entries in FIFO buffer to minimize overall leakage power consumption. The buffer architecture, called IntelliBuffer, has been designed and evaluated in 90 nm and 32 nm CMOS technology. Our synthesized results show that our proposed design is as fast as a conventional buffer structure, while providing the ability to reduce power consumption significantly. When our buffer was used in a Network-on-Chip (NoC) implementation, we obtained 24% leakage savings at 90 nm, and savings of 28% at 32 nm. To further validate the efficacy of our proposed design, we incorporated IntelliBuffer into ViChaR, a recently introduced dynamic buffer management system for NoC routers. Experimental results indicate a marked reduction in ViChaR's leakage power consumption (21% at 90 nm) when IntelliBuffer is employed.
AB - Process Variation (PV) is a consequence of manufacturing imperfections, which may lead to degraded performance or higher leakage power. In this paper, we focus on the design of an intelligent buffer that logically reorders the entries in FIFO buffer to minimize overall leakage power consumption. The buffer architecture, called IntelliBuffer, has been designed and evaluated in 90 nm and 32 nm CMOS technology. Our synthesized results show that our proposed design is as fast as a conventional buffer structure, while providing the ability to reduce power consumption significantly. When our buffer was used in a Network-on-Chip (NoC) implementation, we obtained 24% leakage savings at 90 nm, and savings of 28% at 32 nm. To further validate the efficacy of our proposed design, we incorporated IntelliBuffer into ViChaR, a recently introduced dynamic buffer management system for NoC routers. Experimental results indicate a marked reduction in ViChaR's leakage power consumption (21% at 90 nm) when IntelliBuffer is employed.
UR - http://www.scopus.com/inward/record.url?scp=50249179684&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=50249179684&partnerID=8YFLogxK
U2 - 10.1109/ACSSC.2007.4487459
DO - 10.1109/ACSSC.2007.4487459
M3 - Conference contribution
AN - SCOPUS:50249179684
SN - 9781424421107
T3 - Conference Record - Asilomar Conference on Signals, Systems and Computers
SP - 1402
EP - 1406
BT - Conference Record of the 41st Asilomar Conference on Signals, Systems and Computers, ACSSC
T2 - 41st Asilomar Conference on Signals, Systems and Computers, ACSSC
Y2 - 4 November 2007 through 7 November 2007
ER -