Variation aware placement for FPGAs

Suresh Srinivasan, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)
Original languageEnglish (US)
Title of host publicationProceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
Pages422-423
Number of pages2
Volume2006
DOIs
StatePublished - Oct 9 2006
EventIEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006 - Klarlsruhe, Germany
Duration: Mar 2 2006Mar 3 2006

Other

OtherIEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
CountryGermany
CityKlarlsruhe
Period3/2/063/3/06

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Field programmable gate arrays (FPGA)

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Srinivasan, S., & Narayanan, V. (2006). Variation aware placement for FPGAs. In Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006 (Vol. 2006, pp. 422-423). [1602477] https://doi.org/10.1109/ISVLSI.2006.92
Srinivasan, Suresh ; Narayanan, Vijaykrishnan. / Variation aware placement for FPGAs. Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006. Vol. 2006 2006. pp. 422-423
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Srinivasan, S & Narayanan, V 2006, Variation aware placement for FPGAs. in Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006. vol. 2006, 1602477, pp. 422-423, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006, Klarlsruhe, Germany, 3/2/06. https://doi.org/10.1109/ISVLSI.2006.92

Variation aware placement for FPGAs. / Srinivasan, Suresh; Narayanan, Vijaykrishnan.

Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006. Vol. 2006 2006. p. 422-423 1602477.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Srinivasan S, Narayanan V. Variation aware placement for FPGAs. In Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006. Vol. 2006. 2006. p. 422-423. 1602477 https://doi.org/10.1109/ISVLSI.2006.92