Spin-torque-transfer RAM (STTRAM) is a promising technology for high density on-chip cache due to low standby power and high speed. However, the process variation of STTRAM poses serious challenge to sensing. We propose a non-destructive and low-power sensing scheme that exploits a voltage feedback and boosting technique to develop large sense margin. Monte Carlo simulation results in ST Microelectronics 65-nm technology show that the proposed sensing circuit achieves 807-mV worst case sense margin on average, read access pass yield of σ in typical corner and × reduction in read power compared to conventional voltage sensing.
|Original language||English (US)|
|Number of pages||10|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|State||Published - Jun 2018|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering