ViChaR

A dynamic Virtual Channel Regulator for Network-on-Chip Routers

Chrysostomos A. Nicopoulos, Dongkook Park, Jongman Kim, Vijaykrishnan Narayanan, Mazin S. Yousif, Chitaranjan Das

Research output: Chapter in Book/Report/Conference proceedingConference contribution

221 Citations (Scopus)

Abstract

The advent of deep sub-micron technology has recently highlighted the criticality of the on-chip interconnects. As diminishing feature sizes have led to increases in global wiring delays, Network-on-Chip (NoC) architectures are viewed as a possible solution to the wiring challenge and have recently crystallized into a significant research thrust. Both NoC performance and energy budget depend heavily on the routers' buffer resources. This paper introduces a novel unified buffer structure, called the dynamic Virtual Channel Regulator (ViChaR), which dynamically allocates Virtual Channels (VC) and buffer resources according to network traffic conditions. ViChaR maximizes throughput by dispensing a variable number of VCs on demand. Simulation results using a cycle-accurate simulator show a performance increase of 25% on average over an equal-size generic router buffer, or similar performance using a 50% smaller buffer. ViChaR's ability to provide similar performance with half the buffer size of a generic router is of paramount importance, since this can yield total area and power savings of 30% and 34%, respectively, based on synthesized designs in 90 nm technology.

Original languageEnglish (US)
Title of host publicationProceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-39
Pages333-344
Number of pages12
DOIs
StatePublished - Dec 1 2006
Event39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-39 - Orlando, FL, United States
Duration: Dec 9 2006Dec 13 2006

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture, MICRO
ISSN (Print)1072-4451

Other

Other39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-39
CountryUnited States
CityOrlando, FL
Period12/9/0612/13/06

Fingerprint

Routers
Electric wiring
Simulators
Throughput
Network-on-chip

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Nicopoulos, C. A., Park, D., Kim, J., Narayanan, V., Yousif, M. S., & Das, C. (2006). ViChaR: A dynamic Virtual Channel Regulator for Network-on-Chip Routers. In Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-39 (pp. 333-344). [4041858] (Proceedings of the Annual International Symposium on Microarchitecture, MICRO). https://doi.org/10.1109/MICRO.2006.50
Nicopoulos, Chrysostomos A. ; Park, Dongkook ; Kim, Jongman ; Narayanan, Vijaykrishnan ; Yousif, Mazin S. ; Das, Chitaranjan. / ViChaR : A dynamic Virtual Channel Regulator for Network-on-Chip Routers. Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-39. 2006. pp. 333-344 (Proceedings of the Annual International Symposium on Microarchitecture, MICRO).
@inproceedings{77e077c68fd54db7b12e4ee4c99bc8de,
title = "ViChaR: A dynamic Virtual Channel Regulator for Network-on-Chip Routers",
abstract = "The advent of deep sub-micron technology has recently highlighted the criticality of the on-chip interconnects. As diminishing feature sizes have led to increases in global wiring delays, Network-on-Chip (NoC) architectures are viewed as a possible solution to the wiring challenge and have recently crystallized into a significant research thrust. Both NoC performance and energy budget depend heavily on the routers' buffer resources. This paper introduces a novel unified buffer structure, called the dynamic Virtual Channel Regulator (ViChaR), which dynamically allocates Virtual Channels (VC) and buffer resources according to network traffic conditions. ViChaR maximizes throughput by dispensing a variable number of VCs on demand. Simulation results using a cycle-accurate simulator show a performance increase of 25{\%} on average over an equal-size generic router buffer, or similar performance using a 50{\%} smaller buffer. ViChaR's ability to provide similar performance with half the buffer size of a generic router is of paramount importance, since this can yield total area and power savings of 30{\%} and 34{\%}, respectively, based on synthesized designs in 90 nm technology.",
author = "Nicopoulos, {Chrysostomos A.} and Dongkook Park and Jongman Kim and Vijaykrishnan Narayanan and Yousif, {Mazin S.} and Chitaranjan Das",
year = "2006",
month = "12",
day = "1",
doi = "10.1109/MICRO.2006.50",
language = "English (US)",
isbn = "0769527329",
series = "Proceedings of the Annual International Symposium on Microarchitecture, MICRO",
pages = "333--344",
booktitle = "Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-39",

}

Nicopoulos, CA, Park, D, Kim, J, Narayanan, V, Yousif, MS & Das, C 2006, ViChaR: A dynamic Virtual Channel Regulator for Network-on-Chip Routers. in Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-39., 4041858, Proceedings of the Annual International Symposium on Microarchitecture, MICRO, pp. 333-344, 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-39, Orlando, FL, United States, 12/9/06. https://doi.org/10.1109/MICRO.2006.50

ViChaR : A dynamic Virtual Channel Regulator for Network-on-Chip Routers. / Nicopoulos, Chrysostomos A.; Park, Dongkook; Kim, Jongman; Narayanan, Vijaykrishnan; Yousif, Mazin S.; Das, Chitaranjan.

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-39. 2006. p. 333-344 4041858 (Proceedings of the Annual International Symposium on Microarchitecture, MICRO).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - ViChaR

T2 - A dynamic Virtual Channel Regulator for Network-on-Chip Routers

AU - Nicopoulos, Chrysostomos A.

AU - Park, Dongkook

AU - Kim, Jongman

AU - Narayanan, Vijaykrishnan

AU - Yousif, Mazin S.

AU - Das, Chitaranjan

PY - 2006/12/1

Y1 - 2006/12/1

N2 - The advent of deep sub-micron technology has recently highlighted the criticality of the on-chip interconnects. As diminishing feature sizes have led to increases in global wiring delays, Network-on-Chip (NoC) architectures are viewed as a possible solution to the wiring challenge and have recently crystallized into a significant research thrust. Both NoC performance and energy budget depend heavily on the routers' buffer resources. This paper introduces a novel unified buffer structure, called the dynamic Virtual Channel Regulator (ViChaR), which dynamically allocates Virtual Channels (VC) and buffer resources according to network traffic conditions. ViChaR maximizes throughput by dispensing a variable number of VCs on demand. Simulation results using a cycle-accurate simulator show a performance increase of 25% on average over an equal-size generic router buffer, or similar performance using a 50% smaller buffer. ViChaR's ability to provide similar performance with half the buffer size of a generic router is of paramount importance, since this can yield total area and power savings of 30% and 34%, respectively, based on synthesized designs in 90 nm technology.

AB - The advent of deep sub-micron technology has recently highlighted the criticality of the on-chip interconnects. As diminishing feature sizes have led to increases in global wiring delays, Network-on-Chip (NoC) architectures are viewed as a possible solution to the wiring challenge and have recently crystallized into a significant research thrust. Both NoC performance and energy budget depend heavily on the routers' buffer resources. This paper introduces a novel unified buffer structure, called the dynamic Virtual Channel Regulator (ViChaR), which dynamically allocates Virtual Channels (VC) and buffer resources according to network traffic conditions. ViChaR maximizes throughput by dispensing a variable number of VCs on demand. Simulation results using a cycle-accurate simulator show a performance increase of 25% on average over an equal-size generic router buffer, or similar performance using a 50% smaller buffer. ViChaR's ability to provide similar performance with half the buffer size of a generic router is of paramount importance, since this can yield total area and power savings of 30% and 34%, respectively, based on synthesized designs in 90 nm technology.

UR - http://www.scopus.com/inward/record.url?scp=40349107206&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=40349107206&partnerID=8YFLogxK

U2 - 10.1109/MICRO.2006.50

DO - 10.1109/MICRO.2006.50

M3 - Conference contribution

SN - 0769527329

SN - 9780769527321

T3 - Proceedings of the Annual International Symposium on Microarchitecture, MICRO

SP - 333

EP - 344

BT - Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-39

ER -

Nicopoulos CA, Park D, Kim J, Narayanan V, Yousif MS, Das C. ViChaR: A dynamic Virtual Channel Regulator for Network-on-Chip Routers. In Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-39. 2006. p. 333-344. 4041858. (Proceedings of the Annual International Symposium on Microarchitecture, MICRO). https://doi.org/10.1109/MICRO.2006.50