VL-CDRAM: Variable Line Sized Cached DRAMs

Ananth Hegde, Vijaykrishnan Narayanan, Mahmut Kandemir, Mary Jane Irwin

Research output: Contribution to conferencePaperpeer-review

4 Scopus citations

Abstract

Many of the current memory architectures embed a SRAM cache within the DRAM memory. These architectures exploit a wide internal data bus to transfer an entire DRAM row to the on-memory cache. However, applications exhibit a varying spatial locality across the different DRAM rows that are accessed and buffering the entire row may be wasteful. In order to adapt to the changing spatial locality, we propose a Variable Line size Cached DRAM (VL-CDRAM) that can buffer portions of an accessed DRAM row. Our evaluation shows that the proposed approach is effective in not only reducing the energy consumption but also in improving the performance across various memory configurations.

Original languageEnglish (US)
Pages132-137
Number of pages6
DOIs
StatePublished - Dec 1 2003
EventFirst IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003 - Newport Beach, CA, United States
Duration: Oct 1 2003Oct 3 2003

Other

OtherFirst IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003
CountryUnited States
CityNewport Beach, CA
Period10/1/0310/3/03

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Fingerprint Dive into the research topics of 'VL-CDRAM: Variable Line Sized Cached DRAMs'. Together they form a unique fingerprint.

Cite this