VLSI array architecture with dynamic frequency clocking

N. Ranganathan, Vijaykrishnan Narayanan, N. Bhavanishankar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

In this paper, we describe the concept of dynamic frequency clocking and the design of a linear VLSI array processor, DFLAP, for use in image processing applications. Dynamic frequency clocking enables the chip to operate at different frequencies switching dynamically depending on the instruction being executed. Such a technique facilitates better management of throughput and power requirements in a VLSI system. The applicability of dynamic clocking in pipelined systems is also investigated. The effectiveness of the dynamic frequency architecture is illustrated by mapping several tasks for image processing applications.

Original languageEnglish (US)
Title of host publicationVLSI in Computers and Processors
Editors Anon
PublisherIEEE
Pages137-140
Number of pages4
StatePublished - 1996
EventProceedings of the 1996 International Conference on Computer Design, ICCD'96 - Austin, TX, USA
Duration: Oct 7 1996Oct 9 1996

Other

OtherProceedings of the 1996 International Conference on Computer Design, ICCD'96
CityAustin, TX, USA
Period10/7/9610/9/96

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'VLSI array architecture with dynamic frequency clocking'. Together they form a unique fingerprint.

Cite this