Abstract
In this paper, we describe the concept of dynamic frequency clocking and the design of a linear VLSI array processor, DFLAP, for use in image processing applications. Dynamic frequency clocking enables the chip to operate at different frequencies switching dynamically depending on the instruction being executed. Such a technique facilitates better management of throughput and power requirements in a VLSI system. The applicability of dynamic clocking in pipelined systems is also investigated. The effectiveness of the dynamic frequency architecture is illustrated by mapping several tasks for image processing applications.
| Original language | English (US) |
|---|---|
| Title of host publication | VLSI in Computers and Processors |
| Editors | Anon |
| Publisher | IEEE |
| Pages | 137-140 |
| Number of pages | 4 |
| State | Published - 1996 |
| Event | Proceedings of the 1996 International Conference on Computer Design, ICCD'96 - Austin, TX, USA Duration: Oct 7 1996 → Oct 9 1996 |
Other
| Other | Proceedings of the 1996 International Conference on Computer Design, ICCD'96 |
|---|---|
| City | Austin, TX, USA |
| Period | 10/7/96 → 10/9/96 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering