VLSI design for an adaptive equalizer using a residue number system architecture for magnetic channels

Inseop Lee, W. K. Jenkins

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

This paper presents the design of an experimental ASIC for an all-digital adaptive equalizer for magnetic channels. The equalizer design, which is based on an RNS chip architecture, is presented at a system level, with particular attention to choices of word length, scaling, algorithm performance, and specifics of the RNS modules used to implement the LMS adaptive algorithm. It is believed that the short wordlength and high speed requirements of an adaptive equalizer in this particular application make it ideal for an efficient solution through RNS design techniques.

Original languageEnglish (US)
Title of host publicationMidwest Symposium on Circuits and Systems
Editors Anon
PublisherIEEE
Pages782-785
Number of pages4
Volume2
StatePublished - 1997
EventProceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2) - Sacramento, CA, USA
Duration: Aug 3 1997Aug 6 1997

Other

OtherProceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2)
CitySacramento, CA, USA
Period8/3/978/6/97

    Fingerprint

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Lee, I., & Jenkins, W. K. (1997). VLSI design for an adaptive equalizer using a residue number system architecture for magnetic channels. In Anon (Ed.), Midwest Symposium on Circuits and Systems (Vol. 2, pp. 782-785). IEEE.