VLSI implementation of a 256×256 crossbar interconnection network

Kyusun Choi, William S. Adams

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Scopus citations

Abstract

Despite the fact that a crossbar interconnection network is desirable in parallel processing systems due to its flexibility of configuration and simplicity of control, many of the crossbars developed up to this time are small in size. In this paper, the analysis of VLSI layout size and signal delay of the previous crossbar circuits is presented. Also a circuit with better layout size and signal delay is presented in comparison. Based on the new circuit, the feasibility of the implementation is shown for a 256×256 crossbar on a 1 cm2 CMOS VLSI chip.

Original languageEnglish (US)
Title of host publicationProceedings of the International Conference on Parallel Processing
PublisherPubl by IEEE
Pages289-293
Number of pages5
ISBN (Print)0818626720
StatePublished - Dec 1 1992
EventProceedings of the 6th International Parallel Processing Symposium - Beverly Hills, CA, USA
Duration: Mar 23 1992Mar 26 1992

Publication series

NameProceedings of the International Conference on Parallel Processing
ISSN (Print)0190-3918

Other

OtherProceedings of the 6th International Parallel Processing Symposium
CityBeverly Hills, CA, USA
Period3/23/923/26/92

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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  • Cite this

    Choi, K., & Adams, W. S. (1992). VLSI implementation of a 256×256 crossbar interconnection network. In Proceedings of the International Conference on Parallel Processing (pp. 289-293). (Proceedings of the International Conference on Parallel Processing). Publ by IEEE.