Width minimization in the Single-Electron Transistor array synthesis

Chian Wei Liu, Chang En Chiang, Ching Yi Huang, Chun Yao Wang, Yung Chih Chen, Suman Datta, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

Power consumption has become one of the primary challenges to meet the Moore's law. For reducing power consumption, Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultra-low power consumption during operation. Prior work has proposed an automated mapping approach for SET arrays which focuses on minimizing the number of hexagons in an SET array. However, the area of an SET array is more related to the width. Consequently, in this work, we propose an approach for width minimization of the SET arrays. The experimental results show that the proposed approach saves 26% of width compared with the state-of-the-art for a set of MCNC and IWLS 2005 benchmarks while spending similar CPU time.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe, DATE 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9783981537024
DOIs
StatePublished - 2014
Event17th Design, Automation and Test in Europe, DATE 2014 - Dresden, Germany
Duration: Mar 24 2014Mar 28 2014

Other

Other17th Design, Automation and Test in Europe, DATE 2014
CountryGermany
CityDresden
Period3/24/143/28/14

Fingerprint

Single electron transistors
Electric power utilization
Program processors

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Liu, C. W., Chiang, C. E., Huang, C. Y., Wang, C. Y., Chen, Y. C., Datta, S., & Narayanan, V. (2014). Width minimization in the Single-Electron Transistor array synthesis. In Proceedings - Design, Automation and Test in Europe, DATE 2014 [6800336] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.7873/DATE2014.135
Liu, Chian Wei ; Chiang, Chang En ; Huang, Ching Yi ; Wang, Chun Yao ; Chen, Yung Chih ; Datta, Suman ; Narayanan, Vijaykrishnan. / Width minimization in the Single-Electron Transistor array synthesis. Proceedings - Design, Automation and Test in Europe, DATE 2014. Institute of Electrical and Electronics Engineers Inc., 2014.
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Liu, CW, Chiang, CE, Huang, CY, Wang, CY, Chen, YC, Datta, S & Narayanan, V 2014, Width minimization in the Single-Electron Transistor array synthesis. in Proceedings - Design, Automation and Test in Europe, DATE 2014., 6800336, Institute of Electrical and Electronics Engineers Inc., 17th Design, Automation and Test in Europe, DATE 2014, Dresden, Germany, 3/24/14. https://doi.org/10.7873/DATE2014.135

Width minimization in the Single-Electron Transistor array synthesis. / Liu, Chian Wei; Chiang, Chang En; Huang, Ching Yi; Wang, Chun Yao; Chen, Yung Chih; Datta, Suman; Narayanan, Vijaykrishnan.

Proceedings - Design, Automation and Test in Europe, DATE 2014. Institute of Electrical and Electronics Engineers Inc., 2014. 6800336.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AU - Chiang, Chang En

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AU - Datta, Suman

AU - Narayanan, Vijaykrishnan

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Liu CW, Chiang CE, Huang CY, Wang CY, Chen YC, Datta S et al. Width minimization in the Single-Electron Transistor array synthesis. In Proceedings - Design, Automation and Test in Europe, DATE 2014. Institute of Electrical and Electronics Engineers Inc. 2014. 6800336 https://doi.org/10.7873/DATE2014.135