Write Latency Reduction Techniques of State-of-The-Art Phase Change Memory

Vishal Deep, Tarek Elarabi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Dynamic Random Access Memory (DRAM) has been prevalent over the past few decades as main memory component. The demand of higher memory capacity is increasing continuously, while scaling of DRAM is reaching its boundaries. As we scale DRAM to smaller feature size, difficulties in fabrication, leakage power, and energy consumption become significant. Therefore, memory technologies, which have better scalability feature, will be the future of memory systems. To overcome these limitations, search for a new memory technology is necessary and Phase Change Memory (PCM) is the most promising. PCM is non-volatile memory with better scalability and less leakage power than DRAM. It is a resistance-based memory, which doesn't need to be refreshed. PCM suffers more write latency and less write endurance. The write latency of PCM is higher than its read latency by almost 8 times. A large number of researches have been done on reducing write latency of PCM. This research will focus on studying different approaches and techniques in order to reduce write latency on various aspects. Then, techniques employed to reduce write latency of PCM such as PreSET, Partial-SET, Flip-N-Write, two-stage-write, and two-stage-write-inv are introduced. Conclusively, a performance comparison of each technique is discussed.

Original languageEnglish (US)
Title of host publicationProceedings - UKSim-AMSS 2016
Subtitle of host publication10th European Modelling Symposium on Computer Modelling and Simulation
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages213-217
Number of pages5
ISBN (Electronic)9781509049707
DOIs
StatePublished - May 4 2017
Event10th European Modelling Symposium on Computer Modelling and Simulation, UKSim-AMSS 2016 - Pisa, Italy
Duration: Nov 28 2016Nov 30 2016

Publication series

NameProceedings - UKSim-AMSS 2016: 10th European Modelling Symposium on Computer Modelling and Simulation

Other

Other10th European Modelling Symposium on Computer Modelling and Simulation, UKSim-AMSS 2016
CountryItaly
CityPisa
Period11/28/1611/30/16

Fingerprint

Phase change memory
Phase Change
Latency
Data storage equipment
Random Access
Scalability
Leakage
Durability
Electric power utilization
Energy utilization

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Artificial Intelligence
  • Modeling and Simulation

Cite this

Deep, V., & Elarabi, T. (2017). Write Latency Reduction Techniques of State-of-The-Art Phase Change Memory. In Proceedings - UKSim-AMSS 2016: 10th European Modelling Symposium on Computer Modelling and Simulation (pp. 213-217). [7920253] (Proceedings - UKSim-AMSS 2016: 10th European Modelling Symposium on Computer Modelling and Simulation). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EMS.2016.044
Deep, Vishal ; Elarabi, Tarek. / Write Latency Reduction Techniques of State-of-The-Art Phase Change Memory. Proceedings - UKSim-AMSS 2016: 10th European Modelling Symposium on Computer Modelling and Simulation. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 213-217 (Proceedings - UKSim-AMSS 2016: 10th European Modelling Symposium on Computer Modelling and Simulation).
@inproceedings{5f5d4b3923d8477a9f12229852dc0431,
title = "Write Latency Reduction Techniques of State-of-The-Art Phase Change Memory",
abstract = "Dynamic Random Access Memory (DRAM) has been prevalent over the past few decades as main memory component. The demand of higher memory capacity is increasing continuously, while scaling of DRAM is reaching its boundaries. As we scale DRAM to smaller feature size, difficulties in fabrication, leakage power, and energy consumption become significant. Therefore, memory technologies, which have better scalability feature, will be the future of memory systems. To overcome these limitations, search for a new memory technology is necessary and Phase Change Memory (PCM) is the most promising. PCM is non-volatile memory with better scalability and less leakage power than DRAM. It is a resistance-based memory, which doesn't need to be refreshed. PCM suffers more write latency and less write endurance. The write latency of PCM is higher than its read latency by almost 8 times. A large number of researches have been done on reducing write latency of PCM. This research will focus on studying different approaches and techniques in order to reduce write latency on various aspects. Then, techniques employed to reduce write latency of PCM such as PreSET, Partial-SET, Flip-N-Write, two-stage-write, and two-stage-write-inv are introduced. Conclusively, a performance comparison of each technique is discussed.",
author = "Vishal Deep and Tarek Elarabi",
year = "2017",
month = "5",
day = "4",
doi = "10.1109/EMS.2016.044",
language = "English (US)",
series = "Proceedings - UKSim-AMSS 2016: 10th European Modelling Symposium on Computer Modelling and Simulation",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "213--217",
booktitle = "Proceedings - UKSim-AMSS 2016",
address = "United States",

}

Deep, V & Elarabi, T 2017, Write Latency Reduction Techniques of State-of-The-Art Phase Change Memory. in Proceedings - UKSim-AMSS 2016: 10th European Modelling Symposium on Computer Modelling and Simulation., 7920253, Proceedings - UKSim-AMSS 2016: 10th European Modelling Symposium on Computer Modelling and Simulation, Institute of Electrical and Electronics Engineers Inc., pp. 213-217, 10th European Modelling Symposium on Computer Modelling and Simulation, UKSim-AMSS 2016, Pisa, Italy, 11/28/16. https://doi.org/10.1109/EMS.2016.044

Write Latency Reduction Techniques of State-of-The-Art Phase Change Memory. / Deep, Vishal; Elarabi, Tarek.

Proceedings - UKSim-AMSS 2016: 10th European Modelling Symposium on Computer Modelling and Simulation. Institute of Electrical and Electronics Engineers Inc., 2017. p. 213-217 7920253 (Proceedings - UKSim-AMSS 2016: 10th European Modelling Symposium on Computer Modelling and Simulation).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Write Latency Reduction Techniques of State-of-The-Art Phase Change Memory

AU - Deep, Vishal

AU - Elarabi, Tarek

PY - 2017/5/4

Y1 - 2017/5/4

N2 - Dynamic Random Access Memory (DRAM) has been prevalent over the past few decades as main memory component. The demand of higher memory capacity is increasing continuously, while scaling of DRAM is reaching its boundaries. As we scale DRAM to smaller feature size, difficulties in fabrication, leakage power, and energy consumption become significant. Therefore, memory technologies, which have better scalability feature, will be the future of memory systems. To overcome these limitations, search for a new memory technology is necessary and Phase Change Memory (PCM) is the most promising. PCM is non-volatile memory with better scalability and less leakage power than DRAM. It is a resistance-based memory, which doesn't need to be refreshed. PCM suffers more write latency and less write endurance. The write latency of PCM is higher than its read latency by almost 8 times. A large number of researches have been done on reducing write latency of PCM. This research will focus on studying different approaches and techniques in order to reduce write latency on various aspects. Then, techniques employed to reduce write latency of PCM such as PreSET, Partial-SET, Flip-N-Write, two-stage-write, and two-stage-write-inv are introduced. Conclusively, a performance comparison of each technique is discussed.

AB - Dynamic Random Access Memory (DRAM) has been prevalent over the past few decades as main memory component. The demand of higher memory capacity is increasing continuously, while scaling of DRAM is reaching its boundaries. As we scale DRAM to smaller feature size, difficulties in fabrication, leakage power, and energy consumption become significant. Therefore, memory technologies, which have better scalability feature, will be the future of memory systems. To overcome these limitations, search for a new memory technology is necessary and Phase Change Memory (PCM) is the most promising. PCM is non-volatile memory with better scalability and less leakage power than DRAM. It is a resistance-based memory, which doesn't need to be refreshed. PCM suffers more write latency and less write endurance. The write latency of PCM is higher than its read latency by almost 8 times. A large number of researches have been done on reducing write latency of PCM. This research will focus on studying different approaches and techniques in order to reduce write latency on various aspects. Then, techniques employed to reduce write latency of PCM such as PreSET, Partial-SET, Flip-N-Write, two-stage-write, and two-stage-write-inv are introduced. Conclusively, a performance comparison of each technique is discussed.

UR - http://www.scopus.com/inward/record.url?scp=85020016464&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85020016464&partnerID=8YFLogxK

U2 - 10.1109/EMS.2016.044

DO - 10.1109/EMS.2016.044

M3 - Conference contribution

AN - SCOPUS:85020016464

T3 - Proceedings - UKSim-AMSS 2016: 10th European Modelling Symposium on Computer Modelling and Simulation

SP - 213

EP - 217

BT - Proceedings - UKSim-AMSS 2016

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Deep V, Elarabi T. Write Latency Reduction Techniques of State-of-The-Art Phase Change Memory. In Proceedings - UKSim-AMSS 2016: 10th European Modelling Symposium on Computer Modelling and Simulation. Institute of Electrical and Electronics Engineers Inc. 2017. p. 213-217. 7920253. (Proceedings - UKSim-AMSS 2016: 10th European Modelling Symposium on Computer Modelling and Simulation). https://doi.org/10.1109/EMS.2016.044