Write-optimized reliable design of STT MRAM

Yusung Kim, Sumeet Kumar Gupta, Sang Phill Park, Georgios Panagopoulos, Kaushik Roy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

49 Citations (Scopus)

Abstract

Spin transfer torque magnetic random access memory (STT MRAM) is a promising non-volatile memory due to its outstanding potential for high integration density and excellent scalability. Despite the attractive features, high write current and power is still a major challenge. As a result, the optimization of the memory for write is critical. In this work, we analyze asymmetric write currents in STT MRAMs considering process variations, and identify a potential for write power reduction. We propose circuit design techniques 1) bit-line voltage clamping using a pass transistor and 2) 2T-1R dual source-line bit-cell design, to balance out the asymmetric write currents and optimize the memory design from both write-power and reliability aspects. Our proposed techniques can be easily incorporated with previously proposed design techniques without affecting the bit-cell write-ability, read stability, and performance. We analyze the impact of our proposed techniques on write power and MTJ current density and show 30-68% average write power savings and 4-41% reduction in MTJ current density in STT MRAM.

Original languageEnglish (US)
Title of host publicationISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design
Pages3-8
Number of pages6
DOIs
StatePublished - Sep 4 2012
Event2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12 - Redondo Beach, CA, United States
Duration: Jul 30 2012Aug 1 2012

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Other

Other2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12
CountryUnited States
CityRedondo Beach, CA
Period7/30/128/1/12

Fingerprint

Torque
Data storage equipment
Current density
Scalability
Transistors
Networks (circuits)
Electric potential

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Kim, Y., Gupta, S. K., Park, S. P., Panagopoulos, G., & Roy, K. (2012). Write-optimized reliable design of STT MRAM. In ISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design (pp. 3-8). (Proceedings of the International Symposium on Low Power Electronics and Design). https://doi.org/10.1145/2333660.2333664
Kim, Yusung ; Gupta, Sumeet Kumar ; Park, Sang Phill ; Panagopoulos, Georgios ; Roy, Kaushik. / Write-optimized reliable design of STT MRAM. ISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design. 2012. pp. 3-8 (Proceedings of the International Symposium on Low Power Electronics and Design).
@inproceedings{3f79ccaa8596434eb91eb2fdd318af2e,
title = "Write-optimized reliable design of STT MRAM",
abstract = "Spin transfer torque magnetic random access memory (STT MRAM) is a promising non-volatile memory due to its outstanding potential for high integration density and excellent scalability. Despite the attractive features, high write current and power is still a major challenge. As a result, the optimization of the memory for write is critical. In this work, we analyze asymmetric write currents in STT MRAMs considering process variations, and identify a potential for write power reduction. We propose circuit design techniques 1) bit-line voltage clamping using a pass transistor and 2) 2T-1R dual source-line bit-cell design, to balance out the asymmetric write currents and optimize the memory design from both write-power and reliability aspects. Our proposed techniques can be easily incorporated with previously proposed design techniques without affecting the bit-cell write-ability, read stability, and performance. We analyze the impact of our proposed techniques on write power and MTJ current density and show 30-68{\%} average write power savings and 4-41{\%} reduction in MTJ current density in STT MRAM.",
author = "Yusung Kim and Gupta, {Sumeet Kumar} and Park, {Sang Phill} and Georgios Panagopoulos and Kaushik Roy",
year = "2012",
month = "9",
day = "4",
doi = "10.1145/2333660.2333664",
language = "English (US)",
isbn = "9781450312493",
series = "Proceedings of the International Symposium on Low Power Electronics and Design",
pages = "3--8",
booktitle = "ISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design",

}

Kim, Y, Gupta, SK, Park, SP, Panagopoulos, G & Roy, K 2012, Write-optimized reliable design of STT MRAM. in ISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design. Proceedings of the International Symposium on Low Power Electronics and Design, pp. 3-8, 2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12, Redondo Beach, CA, United States, 7/30/12. https://doi.org/10.1145/2333660.2333664

Write-optimized reliable design of STT MRAM. / Kim, Yusung; Gupta, Sumeet Kumar; Park, Sang Phill; Panagopoulos, Georgios; Roy, Kaushik.

ISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design. 2012. p. 3-8 (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Write-optimized reliable design of STT MRAM

AU - Kim, Yusung

AU - Gupta, Sumeet Kumar

AU - Park, Sang Phill

AU - Panagopoulos, Georgios

AU - Roy, Kaushik

PY - 2012/9/4

Y1 - 2012/9/4

N2 - Spin transfer torque magnetic random access memory (STT MRAM) is a promising non-volatile memory due to its outstanding potential for high integration density and excellent scalability. Despite the attractive features, high write current and power is still a major challenge. As a result, the optimization of the memory for write is critical. In this work, we analyze asymmetric write currents in STT MRAMs considering process variations, and identify a potential for write power reduction. We propose circuit design techniques 1) bit-line voltage clamping using a pass transistor and 2) 2T-1R dual source-line bit-cell design, to balance out the asymmetric write currents and optimize the memory design from both write-power and reliability aspects. Our proposed techniques can be easily incorporated with previously proposed design techniques without affecting the bit-cell write-ability, read stability, and performance. We analyze the impact of our proposed techniques on write power and MTJ current density and show 30-68% average write power savings and 4-41% reduction in MTJ current density in STT MRAM.

AB - Spin transfer torque magnetic random access memory (STT MRAM) is a promising non-volatile memory due to its outstanding potential for high integration density and excellent scalability. Despite the attractive features, high write current and power is still a major challenge. As a result, the optimization of the memory for write is critical. In this work, we analyze asymmetric write currents in STT MRAMs considering process variations, and identify a potential for write power reduction. We propose circuit design techniques 1) bit-line voltage clamping using a pass transistor and 2) 2T-1R dual source-line bit-cell design, to balance out the asymmetric write currents and optimize the memory design from both write-power and reliability aspects. Our proposed techniques can be easily incorporated with previously proposed design techniques without affecting the bit-cell write-ability, read stability, and performance. We analyze the impact of our proposed techniques on write power and MTJ current density and show 30-68% average write power savings and 4-41% reduction in MTJ current density in STT MRAM.

UR - http://www.scopus.com/inward/record.url?scp=84865559700&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84865559700&partnerID=8YFLogxK

U2 - 10.1145/2333660.2333664

DO - 10.1145/2333660.2333664

M3 - Conference contribution

AN - SCOPUS:84865559700

SN - 9781450312493

T3 - Proceedings of the International Symposium on Low Power Electronics and Design

SP - 3

EP - 8

BT - ISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design

ER -

Kim Y, Gupta SK, Park SP, Panagopoulos G, Roy K. Write-optimized reliable design of STT MRAM. In ISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design. 2012. p. 3-8. (Proceedings of the International Symposium on Low Power Electronics and Design). https://doi.org/10.1145/2333660.2333664