Write-optimized reliable design of STT MRAM

Yusung Kim, Sumeet Kumar Gupta, Sang Phill Park, Georgios Panagopoulos, Kaushik Roy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

49 Scopus citations

Abstract

Spin transfer torque magnetic random access memory (STT MRAM) is a promising non-volatile memory due to its outstanding potential for high integration density and excellent scalability. Despite the attractive features, high write current and power is still a major challenge. As a result, the optimization of the memory for write is critical. In this work, we analyze asymmetric write currents in STT MRAMs considering process variations, and identify a potential for write power reduction. We propose circuit design techniques 1) bit-line voltage clamping using a pass transistor and 2) 2T-1R dual source-line bit-cell design, to balance out the asymmetric write currents and optimize the memory design from both write-power and reliability aspects. Our proposed techniques can be easily incorporated with previously proposed design techniques without affecting the bit-cell write-ability, read stability, and performance. We analyze the impact of our proposed techniques on write power and MTJ current density and show 30-68% average write power savings and 4-41% reduction in MTJ current density in STT MRAM.

Original languageEnglish (US)
Title of host publicationISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design
Pages3-8
Number of pages6
DOIs
Publication statusPublished - Sep 4 2012
Event2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12 - Redondo Beach, CA, United States
Duration: Jul 30 2012Aug 1 2012

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Other

Other2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12
CountryUnited States
CityRedondo Beach, CA
Period7/30/128/1/12

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All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Kim, Y., Gupta, S. K., Park, S. P., Panagopoulos, G., & Roy, K. (2012). Write-optimized reliable design of STT MRAM. In ISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design (pp. 3-8). (Proceedings of the International Symposium on Low Power Electronics and Design). https://doi.org/10.1145/2333660.2333664