Write-optimized STT-MRAM bit-cells using asymmetrically doped transistors

Sri Harsha Choday, Sumeet K. Gupta, Kaushik Roy

    Research output: Contribution to journalArticlepeer-review

    14 Scopus citations

    Abstract

    Spin-transfer torque MRAM (STT-MRAM) is a potential candidate for replacing SRAMs in last level on-chip caches. However, it comes with high write power and oxide reliability issues due to large current required to achieve high speed switching. In this letter, we propose a technique to mitigate the conflict between write-ability and write power of STT MRAM using an access transistor with asymmetric doping at the source/drain terminals. Our technique achieves 35% write power reduction at iso-write speed. In addition, the maximum voltage drop across the tunnel barrier in the Magnetic Tunnel Junction reduces by 23% which improves its reliability.

    Original languageEnglish (US)
    Article number6915720
    Pages (from-to)1100-1102
    Number of pages3
    JournalIEEE Electron Device Letters
    Volume35
    Issue number11
    DOIs
    StatePublished - Nov 1 2014

    All Science Journal Classification (ASJC) codes

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

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